基于AT89C51的温度控制系统设计与翻译 - CSDN文库

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XTAL2 ：

Output from the inverting oscillator amplifier. Oscillator CharacteristicsXTAL1 and

XTAL2 are the input and output, respectively, of an inverting amplifier which can be

configured for use as an on-chip oscillator, as shown

in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the dev

ice from an external clock source, XTAL2 should be left unconnected while XTAL1 i

s driven as shown in Figure 2.There are no requirements on the duty cycle of the exter

nal clock signal, since the input to the internal clocking circuitry is through a divide-b

y-two flip-flop, but minimum and maximum voltage high and low time specifications

must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the o

n chip peripherals remain active. The mode is invoked by software. The content of the

on-chip RAM and all the special functions registers remain unchanged during this mo

de. The idle mode can be terminated by any enabled interrupt or by a hardware reset. I

t should be noted that when idle is terminated by a hard ware reset, the device normall

y resumes program execution, from where it left off, up to two machine cycles before

the internal reset algorithm takes control. On-chip hardware inhibits access to internal

RAM in this event, but access to the port pins is not inhibited. To eliminate the possib

ility of an unexpected write to a port pin when Idle is terminated by reset, the instructi

on following the one that invokes Idle should not be one that writes to a port pin or to

external memory.

Power-down Mode

In the power-down mode, the oscillator is stopped, and the instruction that invokes po

wer-down is the last instruction executed. The on-chip RAM and Special Function Re

gisters retain their values until the power-down mode is terminated. The only exit fro

m power-down is a hardware reset. Reset redefines the SFRS but does not change the

on-chip RAM. The reset should not be activated before VCC is restored to its normal

operating level and must be held active long enough to allow the oscillator to restart a

nd stabilize. The AT89C51 code memory array is programmed byte-by byte in either

programming mode. To program any nonblank byte in the on-chip Flash Memory, the

entire memory must be erased using the Chip Erase Mode.

2 Programming Algorithm

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