IEEE 2019 VHDL 语言标准参考手册

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"IEEE Standard for VHDL - 1076-2019" IEEE Std 1076-2019是针对VHDL（Very High Speed Integrated Circuit Hardware Description Language）语言的最新标准参考手册，由IEEE计算机学会的设计自动化标准委员会开发。这个标准是对2008年版本的修订，于2019年9月5日被IEEE系统协会标准委员会批准。该文档通常被授权用于特定的学术机构，如深圳大学城图书馆，并在2021年6月3日下载自IEEE Xplore平台。 VHDL是一种广泛应用的硬件描述语言，主要用于数字电路和系统的设计、验证和实现。它允许工程师以一种结构化和抽象的方式描述电子系统的功能和行为，涵盖了从门级逻辑到系统级设计的多个层次。VHDL的2019版更新可能包含了对语言规范的改进，提高了设计的可读性、可维护性和可重用性，同时也可能适应了现代半导体技术的最新发展。该标准包括了VHDL语言的各个方面，例如： 1. **语法**：定义了VHDL的词汇和句法结构，包括实体、结构体、配置、包、过程、函数等基本元素。 2. **数据类型和操作符**：规定了各种内置数据类型，如数值类型、位串类型以及用户自定义的数据类型。还定义了算术、关系和逻辑操作符，用于描述数字系统的行为。 3. **进程与并发**：VHDL支持并发语句，如进程（process）和并行信号赋值，这使得描述时序逻辑和并行处理成为可能。 4. **包和库**：包用来组织和重用代码，而库则提供了一个机制来管理不同设计的集合。 5. **结构化设计**：VHDL支持模块化设计，允许将复杂系统分解为独立的子单元，这些子单元可以单独设计、验证和复用。 6. **仿真和行为建模**：VHDL不仅可以描述硬件行为，还可以用于行为仿真，帮助设计师在硬件实现前验证设计的功能正确性。 7. **综合和实现**：VHDL设计可以被综合工具转化为特定集成电路工艺的门级或寄存器传输级（RTL）表示，以便于物理实现。 8. **形式验证**：VHDL标准也鼓励形式验证方法，通过数学证明确保设计满足预定的规格。随着技术的进步，VHDL的标准不断更新以适应新的设计挑战，比如高速串行接口、嵌入式处理器和FPGA/CPLD等可编程逻辑器件的使用。2019年的修订可能包含了对这些领域的增强和优化，以提升设计效率和性能。 IEEE Std 1076-2019是VHDL设计者和工程师的重要参考，它不仅定义了语言规范，还为数字系统设计提供了全面的指导和支持，确保了设计的一致性和互操作性。

IEEE Std 1076-2019

IEEE Standard for VHDL Language Reference Manual

Finally, each clause may end with examples, notes, and references to other pertinent clauses.

1.3.2 Syntactic description

The form of a VHDL description is described by means of context-free syntax using a simple variant of the

Backus-Naur form (BNF); in particular:

a) Lowercase words in roman font, some containing embedded underlines, are used to denote syntactic

categories, for example:

formal_port_list

Whenever the name of a syntactic category is used, apart from the syntax rules themselves, spaces

take the place of underlines [thus, “formal port list” would appear in the narrative description when

referring to the syntactic category in item a)].

b) Boldface words are used to denote reserved words, for example:

array

Reserved words shall be used only in those places indicated by the syntax.

c) A production consists of a left-hand side, the symbol “::=” (which is read as “can be replaced by”),

and a right-hand side. The left-hand side of a production is always a syntactic category; the

right-hand side is a replacement rule. The meaning of a production is a textual-replacement rule: any

occurrence of the left-hand side may be replaced by an instance of the right-hand side.

d) A vertical bar (|) separates alternative items on the right-hand side of a production unless it occurs

immediately after an opening brace, in which case it stands for itself, as follows:

letter_or_digit ::= letter | digit

choices ::= choice { | choice }

In the first instance, an occurrence of “letter_or_digit” can be replaced by either “letter” or “digit.”

In the second case, “choices” can be replaced by a list of “choice,” separated by vertical bars [see

item f) for the meaning of braces].

e) Square brackets [ ] enclose optional items on the right-hand side of a production; thus, the following

two productions are equivalent:

return_statement ::= return [ expression ] ;

return_statement ::= return ; | return expression ;

Note, however, that the initial and terminal square brackets in the right-hand side of the production

for signatures (see 4.5.3) are part of the syntax of signatures and do not indicate that the entire

right-hand side is optional.

f) Braces { } enclose a repeated item or items on the right-hand side of a production. The items may

appear zero or more times; the repetitions occur from left to right as with an equivalent left-recursive

rule. Thus, the following two productions are equivalent:

term ::= factor { multiplying_operator factor }

term ::= factor | term multiplying_operator factor

g) If the name of any syntactic category starts with an italicized part, it is equivalent to the category

name without the italicized part. The italicized part is intended to convey some semantic

information. For example, type_name and subtype_name are both syntactically equivalent to name

alone.

h) The term simple_name is used for any occurrence of an identif

ier that already denotes some

declared entity.

3.3 Semantic description

The meaning and restrictions of a particular construct are described with a set of narrative rules immediately

following the syntactic productions. In these rules, an italicized term indicates the definition of that term,

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IEEE Std 1076-2019

IEEE Standard for VHDL Language Reference Manual

and identifiers appearing entirely in uppercase letters refer to definitions in package STANDARD (see

16.3).

The following terms are used in these semantic descriptions with the following meanings:

erroneous: The condition described represents an ill-formed description; however, implementations are not

required to detect and report this condition. Conditions are deemed erroneous only when it is impossible in

general to detect the condition during the processing of the language.

error: The condition described represents an ill-formed description; implementations are required to detect

the condition and report an error to the user of the tool.

illegal: A synonym for “error.”

legal: The condition described represents a well-formed description.

1.3.4 Front matter, examples, notes, references, and annexes

Prior to this subclause are several pieces of introductory material; following Clause 24 are some annexes and

an index. The front matter, annexes (except Annex B), and index serve to orient and otherwise aid the user

of this standard, but are not part of the definition of VHDL; Annex B, however, is normative.

Some clauses of this standard contain examples, notes, and cross-references to other clauses of the standard;

these parts always appear at the end of a clause. Examples are meant to illustrate the possible forms of the

construct described. Illegal examples are italicized. Notes are meant to emphasize consequences of the rules

described in the clause or elsewhere. In order to distinguish notes from the other narrative portions of this

standard, notes are set as enumerated paragraphs in a font smaller than the rest of the text. Cross-references

are meant to guide the user to other relevant clauses of the standard. Examples, notes, and cross-references

are not part of the definition of the language.

1.3.5 Incorporation of Property Specification Language

VHDL incorporates the simple subset of the Property Specification Language (PSL) as an embedded

language for formal specification of the behavior of a VHDL description. PSL is defined by

IEEE Std 1850™-2010.

All PSL constructs that appear in a VHDL description shall conform to the VHDL

flavor of PSL. Within this standard, reference is made to syntactic rules of PSL. Each such reference has the

italicized prefix PSL_ and corresponds to the syntax rule in IEEE Std 1850-2010 with the same name but

without the prefix.

1.4 Word usage

The word shall indicates mandatory requirements strictly to be followed in order to conform to the standard

and from which no deviation is permitted (shall equals is required to).

3, 4

The word should indicates that among several possibilities one is recommended as particularly suitable,

without mentioning or excluding others; or that a certain course of action is preferred but not necessarily

required (should equals is recommended that).

Information on references can be found in Clause 2.

The use of the word must is deprecated and cannot be used when stating mandatory requirements, must is used only to describe

unavoidable situations.

The use of will is deprecated and cannot be used when stating mandatory requirements, will is only used in statements of fact.

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IEEE Std 1076-2019

IEEE Standard for VHDL Language Reference Manual

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE 1076 Open Source Repository.

IEEE Std 754™-2019, IEEE Standard for Floating-Point Arithmetic.

6, 7

IEEE Std 1735™-2014, IEEE Recommended Practice for Encryption and Management of Electronic Design

Intellectual Property (IP).

IEEE Std 1850™-2010, IEEE Standard for Property Specification Language (PSL).

ISO/IEC 8859-1:1998, Information technology—8-bit single-byte coded graphic character sets—Part 1:

Latin alphabet No. 1.

ISO/IEC 9899:2018, Information technology—Programming Languages—C.

ISO/IEC 19501:2005, Information technology—Open Distributed Processing—Unified Modeling Language

(UML) Version 1.4.2.

Jim Lewis, Patrick Lehmann, Robert Gaddi, et al., 2018. “Packages” https://opensource.ieee.org/vasg/Packages/-/archive/release/

Packages-release.zip (supplement to https://opensource.ieee.org/vasg/Packages).

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org).

The IEEE standards or products referred to in this clause are trademarks of the Institute of Electrical and Electronics Engineers, Inc.

ISO publications are available from the International Organization for Standardization (http://www.iso.org/). IEC publications are

available from the International Electrotechnical Commission (http://www.iec.ch). ISO/IEC publications are available from the

American National Standards Institute (http://www.ansi.org/).

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IEEE Std 1076-2019

IEEE Standard for VHDL Language Reference Manual

3. Design entities and configurations

3.1 General

The design entity is the primary hardware abstraction in VHDL. It represents a portion of a hardware design

that has well-defined inputs and outputs and performs a well-defined function. A design entity may

represent an entire system, a subsystem, a board, a chip, a macro-cell, a logic gate, or any level of abstraction

in between. A configuration can be used to describe how design entities are put together to form a complete

design.

A design entity may be described in terms of a hierarchy of blocks, each of which represents a portion of the

whole design. The top-level block in such a hierarchy is the design entity itself; such a block is an external

block that resides in a library and may be used as a component of other designs. Nested blocks in the

hierarchy are internal blocks, defined by block statements (see 11.2).

A design entity may also be described in terms of interconnected components. Each component of a design

entity may be bound to a lower-level design entity in order to define the structure or behavior of that

component. Successive decomposition of a design entity into components, and binding those components to

other design entities that may be decomposed in like manner, results in a hierarchy of design entities

representing a complete design. Such a collection of design entities is called a design hierarchy. The

bindings necessary to identify a design hierarchy can be specified in a configuration of the top-level entity in

the hierarchy.

This clause describes the way in which design entities and configurations are defined. A design entity is

defined by an entity declaration together with a corresponding architecture body. A configuration is defined

by a configuration declaration.

3.2 Entity declarations

3.2.1 General

An entity declaration defines the interface between a given design entity and the environment in which it is

used. It may also specify declarations and statements that are part of the design entity. A given entity

declaration may be shared by many design entities, each of which has a different architecture. Thus, an

entity declaration can potentially represent a class of design entities, each with the same interface.

entity_declaration ::=

entity identifier is

entity_header

entity_declarative_part

[ begin entity_statement_part ]

end [ entity ] [ entity_simple_name ] ;

The entity header and entity declarative part consist of declarative items that pertain to each design entity

whose interface is defined by the entity declaration. The entity statement part, if present, consists of

concurrent statements that are present in each such design entity.

If a simple name appears at the end of an entity declaration, it shall repeat the identifier of the entity

declaration.

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