C8051F50x-F51x
16 Rev. 1.1
1. System Overview
C8051F50x-F51x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features
are listed below. Refer to Table 2.1 for specific product feature selection and part ordering numbers.
High-speed pipelined 8051-compatible microcontroller core (up to 50 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
Controller Area Network (CAN 2.0B) Controller with 32 message objects, each with its own indentifier
mask (C8051F500/2/4/6/8-F510)
LIN 2.1 peripheral (fully backwards compatible, master and slave modes) (C8051F500/2/4/6/8-F510)
True 12-bit 200 ksps 32-channel single-ended ADC with analog multiplexer
Precision programmable 24 MHz internal oscillator that is within ±0.5% across the operating range and
temperature
On-chip Clock Multiplier to reach up to 50 MHz
64 kB (C8051F500/1/2/3/8/9) or 32 kB (C8051F504/5/6/7-F510/1) of on-chip Flash memory
4352 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
External Data Memory Interface (C8051F500/1/4/5 and C8051F508/9-F510/1) with 64 kB address
space
Programmable Counter/Timer Array (PCA) with six capture/compare modules and Watchdog Timer
function
On-chip Voltage Regulator
On-chip Power-On Reset, V
DD
Monitor, and Temperature Sensor
On-chip Voltage Comparator
40, 33, or 25 Port I/O (5 V push-pull)
With on-chip Voltage Regulator, Power-On Reset, V
DD
monitor, Watchdog Timer, and clock oscillator, the
C8051F50x-F51x devices are truly stand-alone System-on-a-Chip solutions. The Flash memory can be
reprogrammed even in-circuit, providing non-volatile data storage, and also allowing field upgrades of the
8051 firmware. User software has complete control of all peripherals, and may individually shut down any
or all peripherals for power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system debugging with-
out occupying package pins.
The devices are specified for 1.8 V to 5.25 V operation over the automotive temperature range (–40 to
+125 °C). The Port I/O and RST
pins can interface to 5 V logic by setting the VIO pin to 5 V. The
C8051F500/1/4/5 devices are available in 48-pin QFP and QFN packages, the C8051F508/9-F510/1 are
available in 40-pin QFN packages, and the C8051F502/3/6/7 devices are available in 32-pin QFP and
QFN packages. All package options are lead-free and RoHS compliant. See Table 2.1 for ordering infor-
mation. Block diagrams are included in Figure 1.1, Figure 1.2, and Figure 1.3.
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