硬连线控制器实现的CPU设计与VHDL代码解析

library ieee;
use ieee.std_logic_1164.all;

entity haha_cpu is
    port(SWA,SWB,SWC,W1,W2,W3,C,CLR,IR7,IR6,IR5,IR4 : in std_logic;
     SKIP,SW_BUSJ,RAM_BUSJ,RS_BUSJ,ALU_BUSJ,LR_WJ,LDIR,LDRi,LDARJ,LDPCJ,LDDR1,LDDR2,
          TJ,ARPP,PCPP,CELJ,CERJ,S0,S1,S2,S3,M,CNJ: out std_logic );

    attribute LOC:string;
    attribute LOC of C: signal is "P71";
    attribute LOC of CLR:signal is "P40";
    attribute LOC of IR7: signal is "P58";
    attribute LOC of IR6: signal is "P55";
    attribute LOC of IR5: signal is "P52";
    attribute LOC of IR4: signal is "P49";
    attribute LOC of SWA :signal is "P50";  
    attribute LOC of SWB :signal is "P53";
    attribute LOC of SWC:signal is "P56";
    attribute LOC of W1:signal is "P2";
    attribute LOC of W2:signal is "P60";
    attribute LOC of W3:signal is "P59";
    attribute LOC of ALU_BUSJ:signal is "P68";
    attribute LOC of RAM_BUSJ:signal is "P76";
    attribute LOC of RS_BUSJ:signal is "P69";
    attribute LOC of SW_BUSJ:signal is "P70";
    attribute LOC of LDRi:signal is "P14";
    attribute LOC of S0:signal is "P18";
    attribute LOC of S1:signal is "P17";
    attribute LOC of S2:signal is "P16";
    attribute LOC of S3:signal is "P15";