Design of AD Controller Customized IP Core Based on FPGA
HUANG xiang sheng
Jiang xi Province Engineering Research Center of New Energy Technology and Equipment,
Nan Chang Jiang xi 30013 China
xshhuang@ecit.cn
Keywords: FPGA; IP Core;AD Controller; SOPC
Abstract. This design elaborates the development process of the custom IP core AD9280 controller
based on FPGA. The design uses FPGA as the core of the microcontroller, realizes the function of AD
controller by adopting the hardware description language,Verilog HDL and encapsulates it to the
custom IP core in the SOPC Builder. In the NIOS II, the application program interface (API) function
of the AD controller software is used to access and control the hardware, the software is written by
using C language. The experimental results show that this custom IP core is feasible and flexible,
fully reflects the advantages of SOPC technology.
Introduction
In recent years, along with the emergence for millions gate level of FPGA (Field Programmable
Gate Array)Chip and complex functional IP core and reconfigurable embedded soft core processor,
SOPC(System On a Programmable Chip)design has become a viable and important design method
[1].
As the basis of the SOPC design, reusable IP (Intellectual Property) core can be defined by EDA
vendors or users or the third party. In general, the IP core provided by EDA vendors or third party is
relatively common in the function, but as making the SOPC design, users often have special
requirements, then we must define IP core to achieve the required functionality. User-defined IP core
has flexibility, tight coupling, high efficiency, low power consumption and other features which have
brought the advantages of SOPC design
[2]
. User-defined IP core for SOPC Builder is flexible and
convenient to implement custom logic.
User custom IP core development process
According to Avalon bus operation user-defined IP core can be divided into different Avalon
Master peripherals, Avalon Slaver peripherals and Avalon Streaming peripherals. Most peripherals
user-developed attribute Avalon Slaver, a development for Avalon Master and Avalon Streaming
peripherals is more complex than Avalon Slaver peripherals, but their development process is the
same. A typical Avalon peripherals development steps
[3]
as follows:
(1) Planning hardware function of components. If micro controller is used to control the
components, then application program interface (API) of the hardware should be planned to access;
(2)On the basis of the hardware and software requirements, define a proper Avalon interface
(typically for Avalon Slaver port);
(3) Using hardware description language to describe the hardware logic. The signal of on-chip bus
Ava1on Slave port is not required, a typical Avalon Slave port contains signals as shown in Table 1.
(4) Separately proving hardware function for component;
(5)Write C header file of the description register to define the image of hardware registers for
software;
(6) Write a driver software for component;
(7) By using the component editor, the source code which passing the test is encapsulated into a
HDL and software file, finish custom component.
Applied Mechanics and Materials Vols. 727-728 (2015) pp 859-862
© (2015) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/AMM.727-728.859
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