TI29F002B：262144位8位闪存内存详细规格

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"TI1-TMS29F002B.pdf" TI的TMS29F002B是一款262144位（32KB）的8位闪存存储器，主要特点包括单电源支持、组织结构、区域化架构、启动代码区架构、扇区保护以及内置的编程/擦除算法。以下是对这些知识点的详细说明： 1. **单电源支持5V 10%读/写操作**： TMS29F002B设计为在5V电源电压范围内工作，允许10%的波动，这使得它在各种电源条件下的稳定性得以保障，简化了系统电源管理。 2. **组织结构：262144位×8位**：这表示芯片总共有262144个8位字节，总共32KB的存储容量。这种组织方式适用于需要中等存储空间的应用，如嵌入式系统或微控制器程序存储。 3. **阵列阻挡架构**：这种架构允许数据以不同的扇区进行组织和管理，包括一个16KB的受保护启动扇区、两个8KB的参数扇区、一个32KB扇区和三个64KB扇区。这种设计提供了灵活性，可以针对不同应用需求选择不同的扇区进行读写操作。 4. **启动代码区架构**：包括T（顶部扇区）和B（底部扇区），这两个启动扇区是用于存放系统启动代码的特殊区域，确保设备在上电时能从预定义的可信位置加载代码。 5. **扇区保护**：提供硬件级别的保护机制，允许用户通过标准编程设备禁用任何扇区的写入或擦除操作，增强了数据的安全性和可靠性。 6. **嵌入式编程/擦除算法**：芯片内置自动预编程和擦除功能，可以对任意扇区进行操作，同时自动验证编程数据，确保写入的数据准确无误。这简化了编程流程，提高了编程效率。 7. **JEDEC标准**：符合JEDEC（Joint Electron Device Engineering Council）行业标准，这意味着该芯片与行业广泛接受的接口和性能规范兼容，易于集成到各种系统设计中。 TMS29F002B是一款适合于需要可靠启动代码存储和灵活数据管理的嵌入式系统的非易失性存储解决方案。其特性集成了高效的数据保护和简便的编程流程，为系统设计者提供了强大且易用的存储选项。此外，需要注意的是，德州仪器（Texas Instruments）的半导体产品在关键应用中的可用性、标准保修及免责声明等内容在数据表的末尾有详细说明，使用前应仔细阅读。

TMS29F002T, TMS29F002B

262144 BY 8-BIT

FLASH MEMORIES

SMJS848 – AUGUST 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

algorithm selection mode

The algorithm-selection mode provides access to a binary code that matches the device with its proper

programming and erase command operations. This mode is activated when V

(11.5 V to 12.5 V) is placed on

address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address

pin A0 from V

to V

. Address pins other than A0, A1, and A6 can be at logic low or at logic high.

The algorithm-selection mode can also be read by using the command register, which is useful when V

is not

available to be placed on address pin A9. Table 4 shows the binary algorithm-selection codes.

Table 4. Algorithm-Selection Codes (5-V Single Power Supply)

†

CODE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer

equivalent code

01H 0 0 0 0 0 0 0 1

TMS29F002T TBD TBD TBD TBD TBD TBD TBD TBD TBD

TMS29F008B TBD TBD TBD TBD TBD TBD TBD TBD TBD

Sector protection 01H 0 0 0 0 0 0 0 1

†

A1 = V

, A6 = V

, CE = V

, OE = V

erasure and programming

Erasure and programming of the ’29F002 are accomplished by writing a sequence of commands using

standard-microprocessor-write timings. The commands are written to a command register and input to the

command-state machine. The command-state machine interprets the command entered and initiates program,

erase, suspend, and resume operations as instructed. The

command-state machine acts as the interface

between the write-state machine and the external-chip operations. The write-state machine controls all voltage

generation, pulse generation, preconditioning, and verification of the contents of the memory. Program and

block-/chip-erase functions are fully automatic. Once the end of a program or erase operation is reached, the

device resets internally to the read mode. If V

drops below the low-voltage-detect level, any programming

or erase operation is aborted and subsequent writes are ignored until the V

level is greater than VLKO. The

control pins must be correct logically to prevent unintentional command writes or programming or erasing.

command definitions

Device operating modes are selected by writing specific address and data sequences into the command

them in the incorrect sequence causes the device to reset to the read mode. The command register does not

occupy an addressable memory location. The register stores the command sequence, along with the address

and data needed by the memory array. Commands are written by setting CE low, OE high, and bringing WE

from high to low. Addresses are latched on the falling edge of WE and data is latched on the rising edge of WE.

Holding WE

low and toggling CE can be used as an alternative. See the switching characteristics of the

write/erase/program-operations section for specific timing information.

PRODUCT PREVIEW

TMS29F002T, TMS29F002B

262144 BY 8-BIT

FLASH MEMORIES

SMJS848 – AUGUST 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

command definitions (continued)

Table 5. Command Definitions

†

COMMAND

BUS

1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE

COMMAND

CYCLES

ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA ADDR DATA

Read/reset 1 XXXH F0H

Read/reset 3 555H AAH 2AAH 55H 555H F0H RA RD

Algorithm

555H

AAH

2AAH

55H

555H

90H

01H

TBD

selection

555H

AAH

2AAH

55H

555H

90H

01H

TBD

Program 4 555H AAH 2AAH 55H 555H A0H PA PD

Chip erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Sector erase 6 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SA 30H

Sector-erase

suspend

1 XXXH B0H Erase suspend valid during sector-erase operation

Sector-erase

resume

1 XXXH 30H Erase resume valid only after erase suspend

LEGEND:

RA = Address of the location to be read

PA = Address of the location to be programmed

SA = Address of the sector to be erased

Addresses A13:A17 select one to seven sectors.

RD = Data to be read at selected address location

PD = Data to be programmed at selected address location

†

Unless otherwise noted, address bits A17 – A11 are don’t care.

read/reset command

The read or reset mode is activated by writing either of the two read/reset command sequences into the

command register. The device remains in this mode until one of the other valid command sequences is input

in the command register. Memory data is available in the read mode and can be read with standard

microprocessor read-cycle timing.

On power up, the device defaults to the read/reset mode. A read/reset command sequence is not required and

memory data is available.

algorithm-selection command

The algorithm-selection command allows access to a binary code that matches the device with the proper

programming and erase command operations. After writing the three-bus-cycle command sequence, the first

byte of the algorithm-selection code can be read from address XX00h. The second byte of the code can be read

from address XX01h (see Table 6). This mode remains in effect until another valid command sequence is written

to the device.

program command

Programming is a four-bus-cycle command sequence. The first three bus cycles put the device into the

program-setup state. The fourth bus cycle loads the address location and the data to be programmed into the

device. The addresses are latched on the falling edge of WE

and the data is latched on the rising edge of WE

in the fourth bus cycle. The rising edge of WE starts the program operation. The embedded programming

function automatically provides needed voltage and timing to program and to verify the cell margin. Any further

commands written to the device during the program operation are ignored.

PRODUCT PREVIEW

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