TI1-TMS29F008B：5V单电源8位闪存芯片详细规格

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"TI1-TMS29F008B.pdf" TI1-TMS29F008B是一款由Texas Instruments（TI）制造的1MB（1048576字节）8位闪存存储器，其详细规格和技术特点如下： 1. **单一电源支持**：该芯片支持5V电源，并且在±10%的电压范围内可稳定工作，确保了在各种应用环境中的可靠运行。 2. **组织结构**：存储器的组织结构为1048576字节x8位，意味着它提供了一百万字节的数据存储空间，每个字节有8位。 3. **阵列块架构**：设计包含一个16K-字节的启动扇区、两个8K-字节的参数扇区、一个32K-字节的扇区以及十五个64K-字节的扇区。用户可以自由组合这些扇区进行擦除操作，并支持全芯片擦除功能。此外，任何扇区都可以被标记为只读，增强了数据保护。 4. **启动代码扇区架构**：分为顶部扇区（T）和底部扇区（B），这种设计考虑到了固件更新和系统启动的需求。 5. **扇区保护**：通过硬件保护机制，允许使用标准编程设备禁用任意组合的扇区，防止未经授权的写入或擦除操作，确保数据安全。 6. **嵌入式编程/擦除算法**：自动预编程和擦除任何扇区，同时自动对指定地址的编程数据进行验证，简化了编程流程并提高了数据可靠性。 7. **JEDEC兼容性**：符合JEDEC（Joint Electron Device Engineering Council）的标准字节引脚布局和EEPROM命令集，这意味着它可以与其他符合JEDEC标准的设备无缝集成。 8. **全自动片上擦除和编程操作**：芯片内置了完整的自动化擦除和编程功能，使得操作更加简便快捷。 9. **耐久性**：该芯片可承受100,000次的编程/擦除循环，显示出了较高的耐用性。 10. **低功耗**：在典型工作条件下，功耗仅为40毫安，适合于对功耗有严格要求的应用场景。 TMS29F008B适用于需要大容量非易失性存储的领域，如嵌入式系统、微控制器应用、数据记录、固件存储等。其强大的扇区保护功能和自动编程/擦除算法使其在嵌入式系统设计中具有很高的价值，同时，其与JEDEC标准的兼容性确保了广泛的硬件互换性和软件兼容性。

TMS29F008T, TMS29F008B

1048576 BY 8-BIT

FLASH MEMORIES

SMJS845A – MARCH 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

operation (continued)

See Table 3 for the operation modes of the TMS29F008T/B.

Table 3. Operation Modes

MODE

FUNCTIONS

†

MODE

CE OE WE A0 A1 A6 A9 RESET DQ0–DQ7

Algorithm-selection mode V

Manufacture-Equivalent Code 01h

(TMS29F008-Byte)

ower su

Device-Equivalent Code D6h

(TMS29F008T-Byte)

ppl

Device-Equivalent Code 58h

(TMS29F008B-Byte)

Read V

A0 A1 A6 A9 V

Data out

Output disable V

X X X X V

Hi-Z

Standby and write inhibit V

X X X X X X V

Hi-Z

Write

‡

A0 A1 A6 A9 V

Data in

Temporary sector unprotect X X X X X X X V

Verify sector protect V

Data out

Hardware reset X X X X X X X V

Hi-Z

Legend:

= Logic low

= Logic high

= 12.0 ± 0.5 V

†

X can be V

or V

‡

See Table 5 for valid address and data during write.

read mode

A logic-low signal applied to the CE

and OE pins allows the output of the TMS29F008T/B to be read. When two

or more ’29F008T/B devices are connected in parallel, the output of any one device can be read without

interference. The CE

pin is for power control and must be used for device selection. The OE pin is for output

control, used to gate the data output onto the bus from the selected device.

The address-access time (t

AVQV

) is the delay from stable address to valid output data. The chip-enable (CE)

access time (t

ELQV

) is the delay from CE low and stable addresses to valid output data. The output-enable

access time (t

GLQV

) is the delay from OE low to valid output data when CE equals logic low and addresses are

stable for at least the duration of t

AVQV

–t

GLQV

standby mode

supply current is reduced by applying a logic-high level on CE and RESET to enter the standby mode. In

the standby mode, the outputs are placed in the high-impedance state. Applying a CMOS logic-high level on

and RESET reduces the current to 100 µA. Applying a TTL logic-high level on CE and RESET reduces the

current to 1 mA. If the ’29F008T/B is deselected during erasure or programming, the device continues to draw

active current until the operation is complete.

output disable

When OE

equals V

or CE equals V

, output from the device is disabled and the output pins (DQ0–DQ7) are

placed in the high-impedance state.

PRODUCT PREVIEW

TMS29F008T, TMS29F008B

1048576 BY 8-BIT

FLASH MEMORIES

SMJS845A – MARCH 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

automatic-sleep mode

The ’29F008 has a built-in feature called automatic-sleep mode to minimize device energy consumption which

is independent of CE

, WE, and OE, and is enabled when addresses remain stable for 300 ns. Typical

sleep-mode current is 100 µA. Sleep mode does not affect output data, which remains latched and available

to the system.

algorithm selection

The algorithm-selection mode provides access to a binary code that matches the device with its proper

programming and erase command operations. This mode is activated when V

(11.5 V to 12.5 V) is placed on

address pin A9. Address pins A1 and A6 must be logic low. Two bytes of code are accessed by toggling address

pin A0 from V

to V

. Address pins other than A0, A1, and A6 can be at logic low or at logic high.

The algorithm-selection mode can also be read by using the command register, which is useful when V

is not

available to be placed on address pin A9. Table 4 shows the binary algorithm-selection codes.

Table 4. Algorithm-Selection Codes (5-V Single Power Supply)

†

CODE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0

Manufacturer-equivalent code 01H 0 0 0 0 0 0 0 1

TMS29F008T-Byte D6H 1 1 0 1 0 1 1 0

TMS29F008B-Byte 58H 0 1 0 1 1 0 0 0

Sector protection 01H 0 0 0 0 0 0 0 1

†

A1 = V

, A6 = V

, CE = OE = V

erasure and programming

Erasure and programming of the ’29F008 are accomplished by writing a sequence of commands using standard

microprocessor write timing. The commands are written to a command register and input to the command-state

machine (CSM). The CSM interprets the command entered and initiates program, erase, suspend, and resume

operations as instructed. The

CSM acts as the interface between the write-state machine (WSM) and

external-chip operations. The WSM controls all voltage generation, pulse generation, preconditioning, and

verification of memory contents. Program and block-/chip-erase functions are fully automatic. Once the end of

a program or erase operation has been reached, the device resets internally to the read mode. If V

drops

below the low-voltage-detect level (V

LKO

), any programming or erase operation is aborted and subsequent

writes are ignored until the V

level is greater than V

LKO

. The control pins must be logically correct to prevent

unintentional command writes or programming or erasing.

command definitions

Device operating modes are selected by writing specific address and data sequences into the command

them in the incorrect sequence causes the device to reset to the read mode. The command register does not

occupy an addressable memory location. The register is used to store the command sequence, along with the

address and data needed by the memory array. Commands are written by setting CE

= V

, OE = V

, and

bringing WE

from logic high to logic low. Addresses are latched on the falling edge of WE and data is latched

on the rising edge of WE

. Holding WE = V

and toggling CE is an alternative method. See the switching

characteristics of the write/erase/program-operations section for specific timing information.

PRODUCT PREVIEW

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