GD25Q32: 32M Flash 存储器技术规格与命令详解

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"GD25Q32数据手册是关于32M闪存存储器GD25Q32的详细技术文档，该器件具备加密功能并支持双倍速读取操作。文档涵盖了其特性、概述、内存组织、操作方式、数据保护、状态寄存器以及一系列的命令描述，包括写使能、写禁止、读状态寄存器、写状态寄存器、读取数据、高速读取、双输出快速读取、四输出快速读取、双I/O快速读取、四I/O快速读取、页编程、块擦除、芯片擦除、深电源下降模式以及设备识别等操作。" GD25Q32是一款由GigaDevice公司生产的32兆字节(MB)的串行闪存存储器，适用于各种嵌入式应用，如微控制器、物联网设备、嵌入式系统等。其主要特点包括： 1. **32M字节的存储容量**：提供大量的非易失性存储空间，用于存储程序代码、配置数据或其他关键信息。 2. **加密功能**：确保数据的安全性，防止未经授权的访问和篡改。 3. **双倍速读取**：相较于标准速度，读取速度翻倍，提高了数据传输效率。内存组织方面，GD25Q32采用了一致的扇区布局，便于管理和擦除操作。文档中详细描述了不同类型的擦除和编程命令： - **页编程(PP)**：允许在单个页面内进行数据编程。 - **块擦除**：包括32K字节块擦除(BE)和64K字节块擦除(BE)，可以快速清除选定的存储区域。 - **芯片擦除(CE)**：擦除整个闪存芯片的所有数据。此外，设备操作涉及到各种控制命令，例如： - **写使能(WREN)** 和 **写禁止(WRDI)**：控制写操作的开启和关闭。 - **读状态寄存器(RDSR)** 和 **写状态寄存器(WRSR)**：用于读取和设置设备的状态，如写保护状态。 - **读取数据(READ)** 和 **高速读取(FASTREAD)**：支持正常和高速模式下读取存储的数据。 - **双输出快速读取(DUALOUTPUTFASTREAD)** 和 **四输出快速读取(QUADOUTPUTFASTREAD)**：通过并行接口提高读取速度。 - **双I/O快速读取(DUALI/OFASTREAD)** 和 **四I/O快速读取(QUADI/OFASTREAD)**：使用双/四I/O引脚实现更快的数据传输。 - **四I/O字节快速读取(QUADI/OWORDFASTREAD)**：进一步优化的高速读取方式。数据保护功能包括状态寄存器，可以设置写保护、就地更新等状态，防止意外修改数据。同时，还提供了深电源下降模式(DP)和从该模式释放的命令，以优化能源效率。最后，用户可以通过特定的命令如 **读制造商标识/设备标识(REM)** 来获取设备的制造商信息和设备型号，以确认设备的身份和兼容性。 GD25Q32数据手册提供了一套全面的操作指南，对于开发人员理解和使用这款闪存存储器至关重要。

Uniform Sector

Dual and Quad Serial Flash GD25Q32B

The GD25Q32B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),

Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the

rising edge of SCLK and data shifts out on the falling edge of SCLK.

Dual SPI

The GD25Q32B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read”

(3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the

standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.

Quad SPI

The GD25Q32B supports Quad SPI operation when using the “Quad Output Fast Read”,” Quad I/O Fast Read”,

“Quad I/O Word Fast Read” (6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the

device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become

bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the

non-volatile Quad Enable bit (QE) in Status Register to be set.

Hold

The HOLD# signal goes low to stop any serial communications with the device, but doesn’t stop the operation of write

status register, programming, or erasing in progress.

The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being

low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge

of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).

The SO is high impedance, both SI and SCLK don’t care during the HOLD operation, if CS# drives high during HOLD

operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and

then CS# must be at low.

Figure1. Hold Condition

5. DATA PROTECTION

The GD25Q32B provide the following data protection methods:

◆ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL bit will

HOLD HOLD

CS#

SCLK

HOLD#

Uniform Sector

Dual and Quad Serial Flash GD25Q32B

return to reset by the following situation:

-Power-Up

-Write Disable (WRDI)

-Write Status Register (WRSR)

-Page Program (PP)

-Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)

◆ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, BP0) bits define the section of the memory

array that can be read but not change.

◆ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP bit.

◆ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from Deep

Power-Down Mode command.

Table1.0 GD25Q32B Protected area size (CMP=0)

Status Register Content Memory Content

BP4

BP3

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

X X 0 0 0 NONE NONE NONE NONE

0 0 0 0 1 63 3F0000H-3FFFFFH 64KB Upper 1/64

0 0 0 1 0 62 to 63 3E0000H-3FFFFFH 128KB Upper 1/32

0 0 0 1 1 60 to 63 3C0000H-3FFFFFH 256KB Upper 1/16

0 0 1 0 0 56 to 63 380000H-3FFFFFH 512KB Upper 1/8

0 0 1 0 1 48 to 63 300000H-3FFFFFH 1MB Upper 1/4

0 0 1 1 0 32 to 63 200000H-3FFFFFH 2MB Upper 1/2

0 1 0 0 1 0 000000H-00FFFFH 64KB Lower 1/64

0 1 0 1 0 0 to 1 000000H-01FFFFH 128KB Lower 1/32

0 1 0 1 1 0 to 3 000000H-03FFFFH 256KB Lower 1/16

0 1 1 0 0 0 to 7 000000H-07FFFFH 512KB Lower 1/8

0 1 1 0 1 0 to 15 000000H-0FFFFFH 1MB Lower 1/4

0 1 1 1 0 0 to 31 000000H-1FFFFFH 2MB Lower 1/2

X X 1 1 1 0 to 63 000000H-3FFFFFH 4MB ALL

1 0 0 0 1 63 3FF000H-3FFFFFH 4KB Top Block

1 0 0 1 0 63 3FE000H-3FFFFFH 8KB Top Block

1 0 0 1 1 63 3FC000H-3FFFFFH 16KB Top Block

1 0 1 0 X 63 3F8000H-3FFFFFH 32KB Top Block

1 0 1 1 0 63 3F8000H-3FFFFFH 32KB Top Block

1 1 0 0 1 0 000000H-000FFFH 4KB Bottom Block

1 1 0 1 0 0 000000H-001FFFH 8KB Bottom Block

1 1 0 1 1 0 000000H-003FFFH 16KB Bottom Block

1 1 1 0 X 0 000000H-007FFFH 32KB Bottom Block

1 1 1 1 0 0 000000H-007FFFH 32KB Bottom Block

Table1.1 GD25Q32B Protected area size (CMP=1)

Status Register Content Memory Content

BP4 BP3 BP2 BP1 BP0 Blocks Addresses Density Portion

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