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Rev. B | Page 16 of 76 | March 2013
ADSP-21467/ADSP-21469
DAI _P
20–1
I/O/T (ipu) High-Z Digital Applications Interface. These pins provide the physical interface to the DAI
SRU. The DAI SRU configuration registers define the combination of on-chip audio-
centric peripheral inputs or outputs connected to the pin and to the pin’s output
enable. The configuration registers of these peripherals then determine the exact
behavior of the pin. Any input or output signal present in the DAI SRU may be routed
to any of these pins. The DAI SRU provides the connection from the serial ports, the
S/PDIF module, input data ports (2), and the precision clock generators (4), to the
DAI_P20–1 pins.
DPI _P
14–1
I/O/T (ipu) High-Z Digital Peripheral Interface. These pins provide the physical interface to the DPI SRU.
The DPI SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin’s output enable. The configu-
ration registers of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the DPI SRU may be routed to any of these pins.
The DPI SRU provides the connection from the timers (2), SPIs (2), UART (1), flags (12),
and general-purpose I/O (9) to the DPI_P14–1 pins.
LDAT0
7–0
LDAT1
7–0
I/O/T (ipd) High-Z Link Port Data (Link Ports 0–1). When configured as a transmitter, the port drives
both the data lines.
LCLK0
LCLK1
I/O/T (ipd) High-Z Link Port Clock (Link Ports 0–1). Allows asynchronous data transfers. When
configured as a transmitter, the port drives LCLKx lines. An external 25 k pull-down
resistor is required for the proper operation of this pin.
LACK0
LACK1
I/O/T (ipd) High-Z Link Port Acknowledge (Link Port 0–1). Provides handshaking. When the link ports
are configured as a receiver, the port drives the LACKx line. An external 25 k pull-
down resistor is required for the proper operation of this pin.
THD_P I Thermal Diode Anode. If unused, can be left floating.
THD_M O Thermal Diode Cathode. If unused, can be left floating.
MLBCLK I Media Local Bus Clock. This clock is generated by the MLB controller that is synchro-
nized to the MOST network and provides the timing for the entire MLB interface.
49.152 MHz at FS = 48 kHz. If unused, connect to ground (see Table 9 on Page 13).
MLBDAT I/O/T in 3 pin
mode. I/T in 5
pin mode.
High-Z Media Local Bus Data. The MLBDAT line is driven by the transmitting MLB device and
is received by all other MLB devices including the MLB controller. The MLBDAT line
carries the actual data. In 5-pin MLB mode, this pin is an input only. If unused, connect
to ground (see Table 9 on Page 13).
MLBSIG I/O/T in 3 pin
mode.
I/T in 5 pin
mode.
High-Z Media Local Bus Signal. This is a multiplexed signal which carries the channel/
address generated by the MLB controller, as well as the command and RxStatus bytes
from MLB devices. In 5-pin mode, this pin is an input only. If unused, connect to ground
(see Table 9 on Page 13).
MLBDO O/T High-Z Media Local Bus Data Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode. This serves as the output data pin in 5-pin mode. If unused, connect to ground
(see Table 9 on Page 13).
MLBSO O/T High-Z Media Local Bus Signal Output (in 5 pin mode). This pin is used only in 5-pin MLB
mode and serves as the output signal pin in 5-pin mode. If unused, connect to ground
(see Table 9 on Page 13).
Table 10. Pin Descriptions (Continued)
Name Type
State During/ After
Reset Description
The following symbols appear in the Type column of Table 10: A = asynchronous, I =input, O = output, S = synchronous, A/D = active drive,
O/D = open-drain, and T = three-state, ipd = internal pull-down resistor, ipu = internal pull-up resistor.
The internal pull-up (ipu) and internal pull-down (ipd) resistors are designed to hold the internal path from the pins at the expected logic levels.
To pull-up or pull-down the external pads to the expected logic levels, use external resistors. Internal pull-up/pull-down resistors cannot be
enabled/disabled and the value of these resistors cannot be programmed. The range of an ipu resistor can be between 26 k–
63 k. The range of an ipd resistor can be between 31 k–85 k. The three-state voltage of ipu pads will not reach to full the V
DD_EXT
level; at
typical conditions the voltage is in the range of 2.3 V to 2.7 V.
In this table, the DDR2 pins are SSTL18 compliant. All other pins are LVTTL compliant.