SDC与TimeQuest接口手册：Tcl API详述

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本参考手册是针对SDC (Software Development Coprocessor) 和 TimeQuest 分析器的专业指南，由Altera Corporation发布。它详尽地介绍了TimeQuest分析器支持的所有SDC命令，以及完整的工具命令语言(Tcl) API。这份文档旨在帮助开发人员和系统工程师深入理解和利用SDC的功能，进行高效的设计和调试工作。 SDC是一种嵌入式软件开发环境，专为Altera的FPGA（现场可编程门阵列）设计而生，它允许用户编写并运行在硬件加速器上执行的自定义软件。通过SDC，开发者可以实现并行处理、数据流处理和高级逻辑控制，从而优化FPGA的设计性能。 TimeQuest，作为Altera提供的一个高级分析工具，主要用于性能分析和系统级验证，能够对硬件设计进行实时监控和测量。通过Tcl API，用户可以直接与TimeQuest进行交互，执行任务调度、触发事件、获取测量数据等操作，这对于理解和优化设计中的瓶颈至关重要。手册的地址位于101 Innovation Drive, San Jose, CA 95134，反映了Altera公司的实际办公地点。版权信息表明，所有内容受2009年Altera Corporation的版权保护，且其中提及的商标和标志，如Altera、Programmable Solutions Company、特定设备名称以及服务名称，均为Altera在全球范围内的注册或未注册商标。此外，手册还提到了Altera的保修政策，即按照标准保修协议，产品会在当前规格下运行，但公司保留随时更新产品和服务的权利。同时，对于手册中所述的信息、产品或服务的任何应用或使用，除非有Altera的书面同意，否则用户需自行承担风险。这份SDC和TimeQuest API参考手册是 FPGA 开发者不可或缺的参考资料，提供了强大的工具集和深入的接口细节，有助于提升设计效率和产品质量。无论是进行低级的硬件编程还是高级的性能分析，理解并熟练运用这些命令和API都是成功项目的关键。

2–6 Chapter 2: SDC and TimeQuest API Package and Commands

sdc

SDC and TimeQuest API Reference Manual © December 2009 Altera Corporation

all_registers

Usage

all_registers

Options

None

Description

Returns a collection of all regisers in the design.

Example

project_open chiptrip

create_timing_netlist

foreach_in_collection reg [all_registers] {

puts [get_register_info -name $reg]

}

report_timig -from [all_regisers] -to [all_registers]

delete_timing_netlist

project_close

Chapter 2: SDC and TimeQuest API Package and Commands 2–7

sdc

create_clock

Usage

create_clock [-add] [-name <clock_name>] -period <value> [-waveform <edge_list>]

Options

-add: Adds clock to a node with an existing clock

-name <clock_name>: Clock name of the created clock

-period <value>: Speed of the clock in terms of clock period

-waveform <edge_list>: List of edge values

<targets>: List or collection of targets

Description

Defines a clock. If the -name option is not used, the clock name is the same as the first target in the list or

collection. The clock name is used to refer to the clock in other commands.

The -period option specifies the clock period. It is also possible to use this option to specify a frequency to

define the clock period. This can be done by using -period option followed by either <frequency>MHz or

"<frequency> MHz". However, this is a TimeQuest-only extension and makes the SDC syntax

non-standard.

The -waveform option specifies the rising and falling edges (duty cycle) of the clock, and is specified as a

list of two time values: the first rising edge and the next falling edge. The rising edge must be within the

range [0, period]. The falling edge must be within one clock period of the rising edge. The waveform

defaults to (0, period/2).

If a clock with the same name is already assigned to a given target, the create_clock command will

overwrite the existing clock. If a clock with a different name exists on the given target, the create_clock

command will be ignored unless the -add option is used. The -add option can be used to assign multiple

clocks to a pin or port.

If the target of the clock is internal (i.e. not an input port), the source latency is zero by default.

If a clock is on a path after another clock, then it blocks or overwrites the previous clock from that point

forward.

The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the

appropriate type. The values used must follow standard Tcl or TimeQuest-extension substitution rules.

See the help for use_timequest_style_escaping for details.

Example

# Create a simple 10ns with clock with a 60% duty cycle

create_clock -period 10 -waveform {0 6} -name clk [get_ports clk]

# Create a clock with a falling edge at 2ns, rising edge at 8ns,

# falling at 12ns, etc.

create_clock -period 10 -waveform {8 12} -name clk [get_ports clk]

# Assign two clocks to an input port that are switched externally

create_clock -period 10 -name clk100Mhz [get_ports clk]

create_clock -period 6.667 -name clk150Mhz -add [get_ports clk]

# Two ways to use MHz to define clock period (TimeQuest only)

create_clock -period 250MHz -name clk250MHz [get_ports clk]

create_clock -period "250 MHz" -name clk250MHz [get_ports clk]

2–8 Chapter 2: SDC and TimeQuest API Package and Commands

sdc

SDC and TimeQuest API Reference Manual © December 2009 Altera Corporation

create_generated_clock

Usage

create_generated_clock [-add] [-divide_by <factor>] [-duty_cycle <percent>]

[-edge_shift <shift_list>] [-edges <edge_list>] [-invert] [-master_clock <clock>]

[-multiply_by <factor>] [-name <clock_name>] [-offset <time>] [-phase <degrees>]

-source <clock_source> <targets>

Options

-add: Add clock to existing clock node

-divide_by <factor>: Division factor

-duty_cycle <percent>: Specifies the duty cycle as a percentage of the clock

period--accepts floating point values

-edge_shift <shift_list>: List of edge shifts

-edges <edge_list>: List of edge values

-invert: Invert the clock waveform

-master_clock <clock>: Specifies clock of the source node

-multiply_by <factor>: Multiplication factor

-name <clock_name>: Name of generated clock

-offset <time>: Specifies the offset as an absolute time shift

-phase <degrees>: Specifies the phase shift in degrees

-source <clock_source>: Source node for the generated clock

<targets>: List or collection of targets

Description

Defines an internally generated clock. If -name is not specified, the clock name is the same as the first

target in the list or collection. The clock name is used to refer to the clock in other commands.

If a clock with the same name is already assigned to a given target, the create_generated_clock command

will overwrite the existing clock. If a clock with a different name exists on the given target, the

create_generated_clockcommand will be ignored unless the -add option is used. The -add option can be

used to assign multiple clocks to a pin or port, and is recommended be used with -master_clock option.

The source of the generated clock, specified by -source, is a port, pin, register, or net in the design. All

waveform modifications are relative to this point. If more than one clock feeds the source node, the

-master_clock option must be used to specify which clock to modify.

The source latency of the generated clock is based on the clock network of the generated clock, and not the

clock network of the node specified using -source. This latency is added to any source latency of the

master clock.

The -divide_by, -multiply_by, -invert, -duty_cycle, -edges, and -edge_shift options modify the waveform

relative to the waveform at the source node.

Clock division and multiplication, using -divide_by and -multiply_by, is performed relative to the first

rising edge. Clock division is based on edges in the master clock waveform, and scaled if the division is an

odd number. Use the -duty_cycle option to specify the new duty cycle for clock multiplication. Use the

-phase option to specify any phase shift relative to the new clock period. Use the -offset option to specify

an arbitrary offset or time shift. Use the -invert option to invert the waveform.

Chapter 2: SDC and TimeQuest API Package and Commands 2–9

sdc

Clock generation can also be specified with the -edges and -edge_shift options. The -edges option accepts a

list of three numbers specifying the master clock edges to use for the first rising edge, the next falling edge,

and next rising edge. Edges of the master clock are labeled according to the first rising edge (1), next falling

edge (2), next rising edge (3), etc. For example, a basic clock divider can be specified equivalently with

-divide_by 2 or -edges {1 3 5}. The -edge_shift option accepts a list of three time values, the amount to shift

each of the three edges.

The value of the targets is either a collection or a Tcl list of wildcards used to create a collection of the

appropriate type. The values used must follow standard Tcl or TimeQuest-extension substitution rules.

See the help for use_timequest_style_escaping for details.

Example

# Create a clock and a divide-by-2 generated clock

create_clock -period 10 [get_ports clk]

create_generated_clock -divide_by 2 -source [get_ports clk] -name clkdiv \

[get_registers clkdiv]

# An equivalent generated clock

create_generated_clock -edges {1 3 5} -source [get_ports clk] -name \

clkdiv [get_registers clkdiv]

# Specify a clock multipler with a 60% duty cycle

create_generated_clock -multiply_by 2 -duty_cycle 60 \

[get_pins clkmult|combout]

# Specify an inverted divide-by-2 clock relative to the output of the

# source clock

create_generated_clock -divide_by 2 -invert -source [get_ports clk] -name \

nclkdiv [get_registers clkdiv]

# Specify a divide-by-2 clock with a 90-degree phase shift

create_generated_clock -divide_by 2 -phase 90 -source [get_ports clk] \

-name clkdiv [get_registers clkdiv]

# Assign two clocks to an input port that are switched externally,

# along with an internal clock divider.

create_clock -period 10 -name clk100Mhz [get_ports clk]

create_clock -period 6.667 -name clk150Mhz -add [get_ports clk]

create_generated_clock -divide_by 2 -name clk50Mhz -source [get_ports \

clk] -master_clock clk100Mhz -add [get_registers clkdiv]

create_generated_clock -divide_by 2 -name clk75Mhz -source [get_ports \

clk] -master_clock clk150Mhz -add [get_registers clkdiv]

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