IEEE1588-2008：精确时钟同步协议标准

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"IEEE1588精确时间同步协议原文，英文版，第二版" IEEE1588协议，全称为“IEEE Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems”，是一种用于网络化测量和控制系统中的精密时钟同步协议。这个标准由IEEE（电气与电子工程师协会）制定，并在2008年进行了修订，即IEEEStd1588-2008，是对2002年版本的更新。该协议的主要目标是解决网络通信、本地计算和分布式对象技术实现的测量和控制系统中的时钟同步问题。它特别适用于通过包交换网络进行通信的系统，允许不同精度、分辨率和稳定性的时钟在同一系统中进行协同工作，实现系统级的同步。 IEEE 1588协议的核心功能包括以下几个方面： 1. **主从时钟模型**：协议定义了主时钟和从时钟的概念，主时钟负责提供准确的时间参考，从时钟则通过网络接收时间信息并调整自身的时钟，以保持与主时钟的一致性。 2. **报文传输**：协议使用特定的报文（如PTP事件消息和通用消息）在网络中传递时间戳信息，这些报文包含了发送时间和接收到的时间，从而可以计算出网络延迟。 3. **时间戳处理**：每个时钟节点对收到的报文进行时间戳记录，以便计算出报文在网络中的传播延迟，进而更精确地调整自身时钟。 4. **同步算法**：协议提供了几种同步算法，如Best Master Clock Algorithm (BMCA)，用于确定网络中的最佳主时钟，确保系统中的所有时钟都能获得最准确的时间源。 5. **校准和补偿**：协议允许对网络延迟进行校准和补偿，以减少由于网络抖动和延迟引起的同步误差。 6. **性能监测**：IEEE 1588还规定了性能监控机制，以评估系统同步的精度和稳定性，便于系统的维护和优化。 7. **兼容性和扩展性**：该标准考虑到了不同硬件和软件平台的兼容性，同时设计了一定的扩展性，可以适应未来可能出现的新技术和应用场景。 IEEE 1588协议广泛应用于电力系统、自动化控制、轨道交通、航空航天、电信网络等需要高精度时间同步的领域，对于确保系统的可靠运行和高效协调至关重要。它的实施提高了网络操作的精准度，降低了因时间不一致引发的错误和问题。

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Table 105 ⎯Translation of flagField from version 2 to version 1 ...................................................... 181

Table 106 ⎯Version 2 fields with no version 1 counterpart............................................................... 182

Table 107 ⎯Version 1 fields with no version 2 counterpart............................................................... 183

Table 108 ⎯Name correspondence..................................................................................................... 183

Table 109 ⎯Mixed system restrictions............................................................................................... 184

Table B.1⎯Relationships between timescales........................................................................................... 199

Table C.1⎯Interpretation of Figure C.1 key values .................................................................................. 202

Table C.2⎯Interpretation of Figure C.2 key values .................................................................................. 203

Table C.3⎯Interpretation of Figure C.3 key values .................................................................................. 205

Table C.4⎯Interpretation of Figure C.4 key values .................................................................................. 207

Table C.5⎯Interpretation of Figure C.5 key values .................................................................................. 209

Table C.6—Interpretation of Figure C.6 key values .................................................................................. 210

Table C.7—Interpretation of Figure C.7 key values .................................................................................. 211

Table C.8—Interpretation of Figure C.8 key values .................................................................................. 213

Table C.9—Interpretation of Figure C.9 key values .................................................................................. 215

Table C.10—Interpretation of Figure C.10 key values............................................................................... 217

Table C.11—Interpretation of Figure C.11 key values............................................................................... 218

Table D.1⎯IPv4 multicast addresses......................................................................................................... 219

Table D.2⎯transportSpecific field values ................................................................................................. 220

Table E.1⎯IPv6 multicast addresses ......................................................................................................... 222

Table F.1⎯Multicast MAC addresses ....................................................................................................... 223

Table F.2⎯Ethernet transport specific field............................................................................................... 224

Table G.1⎯DeviceNet clockIdentity octets 0 through 7............................................................................ 226

Table G.2⎯DeviceNet headers for all PTP message packets .................................................................... 226

Table H.1⎯ControlNet clockIdentity octets 2 through 7........................................................................... 228

Table I.1⎯Mapping of messages............................................................................................................... 231

Table I.2⎯IEEE 802.3 DLPDU syntax ..................................................................................................... 232

Table I.3⎯Multicast MAC address............................................................................................................ 233

Table I.4⎯LT (Length/Type)..................................................................................................................... 234

Table I.6⎯Mapping of the parameter and attribute names ........................................................................ 235

Table I.7⎯Translation of flagField from PTP version 2 to PROFINET.................................................... 236

Table K.1⎯flagField.SECURE flag .......................................................................................................... 242

Table K.2⎯AUTHENTICATION TLV .................................................................................................... 260

Table K.3⎯algorithmId values .................................................................................................................. 261

Table K.4⎯ICV and pad length................................................................................................................. 261

Table K.5⎯AUTHENTICATION_CHALLENGE TLV .......................................................................... 262

xvi

FIGURES

Figure 1 ⎯Mealy state transition diagram .............................................................................................. 10

Figure 2 ⎯Model of an ordinary clock ................................................................................................... 19

Figure 3 ⎯Model of a boundary clock.................................................................................................... 21

Figure 4 ⎯Model of an end-to-end transparent clock ............................................................................. 22

Figure 5 ⎯End-to-end residence time correction model......................................................................... 23

Figure 6 ⎯Combined ordinary and end-to-end transparent clock........................................................... 25

Figure 7 ⎯Model of a peer-to-peer transparent clock............................................................................. 27

Figure 8 ⎯Peer-to-peer residence time and link delay correction model................................................ 28

Figure 9 ⎯Combined ordinary and peer-to-peer transparent clock. ....................................................... 30

Figure 10 ⎯Simple master−slave clock hierarchy ............................................................................... 32

Figure 11 ⎯Pruned mesh topology ...................................................................................................... 33

Figure 12 ⎯Basic synchronization message exchange ........................................................................ 34

Figure 13 ⎯Link delay measurement................................................................................................... 35

Figure 14 ⎯Timestamp generation model............................................................................................ 36

Figure 15 ⎯Hierarchical topology ....................................................................................................... 37

Figure 16 ⎯Linear topology................................................................................................................. 38

Figure 17 ⎯Multiply connected topology............................................................................................ 39

Figure 18 ⎯Bridging disparate technologies........................................................................................ 40

Figure 19 ⎯Definition of latency constants ......................................................................................... 45

Figure 20 ⎯Propagation asymmetry .................................................................................................... 47

Figure 21 ⎯Port model ........................................................................................................................ 48

Figure 22 ⎯Scaled log variance hysteresis .......................................................................................... 60

Figure 23 ⎯State machine for a full implementation........................................................................... 78

Figure 24 ⎯State machine for a slave-only implementation................................................................ 79

Figure 25 ⎯STATE_DECISION_EVENT logic ................................................................................. 81

Figure 26 ⎯State decision algorithm ................................................................................................... 87

Figure 27 ⎯Data set comparison algorithm, part 1 .............................................................................. 89

Figure 28 ⎯Data set comparison algorithm, part 2 .............................................................................. 90

Figure 29 ⎯Receipt of Announce message logic................................................................................. 96

Figure 30 ⎯Receipt of Sync message logic ......................................................................................... 98

Figure 31 ⎯Receipt of Follow_Up message logic ............................................................................. 100

Figure 32 ⎯Receipt of Delay_Req message logic ............................................................................. 101

Figure 33 ⎯Receipt of Delay_Resp message logic............................................................................ 103

Figure 34 ⎯Delay request-response path length measurement.......................................................... 110

xvii

Figure 35 ⎯Peer delay link measurement .......................................................................................... 113

Figure 36 ⎯Permitted mixed system configuration ........................................................................... 183

Figure 37 ⎯Profile print form............................................................................................................ 186

Figure C.1⎯Master, end-to-end, and slave one-step clocks; no asymmetry correction ............................ 201

Figure C.2⎯Master, end-to-end, and slave one-step clocks; with asymmetry correction ......................... 202

Figure C.3⎯Master two-step and end-to-end transparent and slave one-step clocks; with asymmetry

correction.................................................................................................................................................... 204

Figure C.4⎯Master and end-to-end transparent, two-step, and one-step, slave clocks; with asymmetry

correction.................................................................................................................................................... 206

Figure C.5⎯One-step master, two-step end-to-end transparent, and one-step slave clocks; with asymmetry

correction.................................................................................................................................................... 208

Figure C.6—One-step peer responder, end-to-end transparent, and peer requestor clocks; with asymmetry

correction.................................................................................................................................................... 210

Figure C.7—One-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks;

with asymmetry correction ......................................................................................................................... 211

Figure C.8—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 1; with asymmetry correction.......................................................................................................... 212

Figure C.9—Two-step peer responder, two-step end-to-end transparent, and one-step peer requestor clocks:

option 2; with asymmetry correction.......................................................................................................... 214

Figure C.10—Two-step peer responder, one-step end-to-end transparent, and one-step peer requestor

clocks: option 2; with asymmetry correction.............................................................................................. 216

Figure C.11—One-step peer master, two-step peer-to-peer transparent, and one-step peer slave clocks; time

computation................................................................................................................................................ 217

Figure G.1⎯ Event message timestamp point ........................................................................................... 225

Figure I.1⎯PROFINET region combined with domains........................................................................... 231

Figure K.1⎯PTP secure message processing ............................................................................................ 252

Figure K.2⎯Challenge processing............................................................................................................. 254

Figure K.3⎯Secure transmit processing.................................................................................................... 256

Figure K.4⎯Secure event processing ........................................................................................................ 258

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