CNFET驱动的三重脉冲可逆计数器设计：新颖高效

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本文主要探讨了基于碳纳米管场效应晶体管(Carbon Nanotube Field-Effect Transistors, CNFET)的三重脉冲可逆计数器的设计。在当前信息社会日益发展的背景下，集成电路技术已经进入了纳米尺度，传统的二进制逻辑电路面临着性能和效率的挑战。多值逻辑作为改进方案，被提出以增强电路的灵活性和处理能力。设计者首先分析了一种新颖的脉冲可逆计数器的工作原理和结构，这种设计利用了CNFET的独特特性。他们着重设计了一种具有复位端和置位端的三态脉冲触发器，这是设计的关键组件。通过对开关信号理论的应用，确保了触发器的高精度和低功耗操作。接下来，文中介绍了上下计数电路和借位/借出控制电路的设计，这些电路的集成使得整个计数器能够实现三态输出，从而实现了计数过程中的非破坏性状态转换。这在需要节省电能和减少噪声干扰的应用中具有显著优势。通过HSPICE（高级模拟程序接口）进行仿真，结果显示与基于JKL触发器的计数器相比，基于CNFET的三重脉冲可逆计数器在性能上有了显著提升，降低了36.4%的能耗，证明了新型设计在小型化、低功耗和高效率方面的潜力。本文的研究不仅深入理解了CNFET在多值逻辑设计中的应用，还展示了其在可逆计数器设计中的实际效能，对于推动纳米级集成电路技术的发展具有重要意义。未来的研究可以进一步探索CNFET在更多复杂逻辑电路和系统中的应用，以满足不断增长的电子设备对高效能、低功耗的需求。

Design of Ternary Pulsed Reversible Counter based on CNFET

Yaopeng Kang

, Pengjun Wang

1,2*

Yuejun Zhang

, Gang Li

Institute of Circuits and Systems, Ningbo University, Ningbo, 315211, China

College of Physics and Electronic Information Engineering, Wenzhou University, Wenzhou 325035, China

* Email:wangpengjun@nbu.edu.cn

Abstract

By analyzing the principle and structure of A novel

pulsed reversible counter are designed with Carbon

Nanotube Field Effect Transistors(CNFET). Firstly, the

ternary pulsed D trigger with reset port and set port is

up/down circuit, carry/borrow controlled circuit are

designed, respectively. Based on the design above, the

four bit ternary reversible counter with CNFET is

achieved. After simulating by HSPICE, the result show

that proposed circuit decreased by 36.4 percent compare

with counter based on JKL flip-flop.

1. Introduction

With the development of information society,

integrated circuit technology has stepped into nano scale.

Traditional digital circuits are designed by binary logic

background, multi-valued logic appears for improving

the integration because its information carried by a line

more than binary logic, such as ternary logic. Compared

with binary logic circuit, a ternary logic circuit needs

fewer operations and less gates in accomplishing the

same functionality[2].

Single wall carbon nanotube has 1-D ballistic

transport property which allow free electrons move in

long distances along the direction of the tube without

any scattering[3]. It makes CNFET have the

characteristics of high-speed and low-power so that

CNFET is suitable for designing circuit than MOSFET.

What s more, in multi-threshold circuit designed, the

MOSFET need additional bias voltages to its base or

bulk terminal which means an additional power supply

or more to change the threshold voltage. As a substitute

for MOSFET, the Carbon Nano Tube Field Effect

Transistor(CNTFET) can only adjust the diameter of the

CNTs to change its threshold voltage[4], CNFET is more

suitable for designing multivalued logic circuit than

MOSFET.

The counter is necessary in digital logic circuit, it can

record the number of impulse and digital operation. The

counter is composed of logic gates and triggers.

Combined multi-valued logic with CNFET, the pulsed

reversible counter is proposed by designing ternary

pulsed D trigger, counter up/down counting circuit and

carry/borrow circuit, respectively.

2. Design of ternary pulsed circuit with reset port and

set port

The pulsed D flip-flop is composed of pulse generator

and D latch, it transmits signal from input only when the

pulse come[5]. Compared with master-slave trigger, the

pulsed flip-flop has simple structure and low delay, so

that counter designed by pulsed flip-flop can simplified

the structure to thrift the extra hardware overhead.

Table1 show truth table of ternary pulsed D flip-flops

with the reset port and the set port.

Table 1. Truth table of ternary pulsed D flip-flops with

the reset port and the set port

clk R S D Q

× 0 × × 0

× 2 2 × 2

0/2 2 0 × hold

2 0 0 0

2 0 1 1

2 0 2 2

Where R is reset signal, S is set signal, D and Q

denote the input and output of the decoder for the D

flip-flop,

means random signal and means rising

edge. When the signal R=0, the output Q= 0; When the

signal R=2 and S=2, the output Q=2; When the signal

R=2 and S=0, the D flip-flop work normally. Combine

with switching signal theory, the switch level expression

of the ternary pulsed D flip-flop is show as follow:

Q R R S Q clkp

D clkp D D clkp

D clkp

(1)

When the signal R=0, the formula 0*R

0.5

=0 Q =0;

When the signal R=2 and S=2, the formula

2*(

0.5

S)=2, Q =2; When the signal R=2 and S=0, the

output Q =D.

In integrated circuit design, the logic 1 cannot be

identified by field effect transistor individually. For

distinguishing logic 1 , the literal circuit for logic 1 is

designed. The truth table of ternary literal operation is

displayed in table 2.

Table 2. Truth table of ternary literal operation

0 2 2

1 0 0

2 0 2

395

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