"DS100DF410: 以太网重定时器与光模块的解决方案"

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The TI-DS100DF410.pdf is a comprehensive document detailing the features and specifications of the DS100DF410, a highly advanced Ethernet re-timer. This re-timer is designed for use in a variety of networking applications, such as line cards, switch fabrics, and backplane/midplane systems. It is also compatible with various optical modules, including passive copper ASICs. The DS100DF410 is capable of cleaning noisy signals and restoring them to their original integrity, ensuring reliable data transmission at 10GbE speeds. It features four channels, each capable of processing data at 10GbE rates. The re-timer is equipped with connectors compatible with SFP (SFF8431) and QSFP optical modules, providing a versatile interface for different networking setups. Overall, the DS100DF410 is a powerful and versatile Ethernet re-timer that offers industry-leading performance and reliability. Its advanced features make it an ideal choice for high-speed networking applications where signal integrity is paramount. For more information on the DS100DF410, refer to the product folder and sample documentation provided.

0 1 2 3 4 5 6 7 8 9 10

-1.0

-0.5

0.0

0.5

1.0

VOD (V)

TIME (UI)

DS100DF410

ZHCS749B –JANUARY 2012–REVISED JANUARY 2015

www.ti.com.cn

Feature Description (continued)

7.3.3 CTLE

The CTLE in the DS125DF410 is a fully adaptive equalizer with optional limiting stage. The CTLE adapts

according to a Figure of Merit (FOM) calculation during the lock acquisition process. Once the CDR has locked

and the CTLE has been adapted, the CTLE boost level will be frozen until a manual re-adapt command is issued

or until the CDR re-enters the lock acquisition state. The CTLE is typically readapted by resetting the CDR. The

CTLE consists of 4 stages, with each stage having 2-bit boost control. This allows for 256 different stage-boost

combinations. The CTLE adaption algorithm allows the CTLE to adapt through 32 of these stage-boost

combinations. These 32 stage-boost combinations comprise the EQ Table in the channel registers; see channel

registers 0x40 through 0x5F. This EQ Table can be reprogrammed to support up to 32 of the 256 stage-boost

settings.

CTLE boost levels are determined by summing the boosts levels of the 4 stages. Different stage-boost

combinations that sum to the same number will have approximately the same boost level, but will result in a

different shape for the EQ transfer function (boost curve).

The fourth stage in the CTLE can be programmed through the SMBus interface to become a limiting stage rather

than a linear stage. This is useful in some applications, but it should not be typically used in combination with the

DFE.

7.3.4 DFE

A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk,

reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the

selected adapt mode. The DFE can be manually configured to specified tap polarities and tap weights.

The DFE taps are all feedback taps with 1UI spacing. Each tap has a specified boost weight range and polarity

bit.

7.3.5 Clock and Data Recovery

The DS100DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming

data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit

transitions. This process produces a recovered clock with jitter which is greatly reduced for jitter frequencies

outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the

DS100DF410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter

budget for the system.

7.3.6 Output Driver

The output driver is capable of driving variable output voltages with variable amounts of analog de-emphasis.

The output voltage and de-emphasis level can be configured by writing registers over the SMBus. The

DS100DF410 cannot determine independently the appropriate output voltage or de-emphasis setting, so the user

is responsible for configuring these parameters. They can be set for each channel independently.

An idealized transmit waveform with analog de-emphasis applied is shown in Figure 4.

Figure 4. Idealized De-Emphasis Waveform

DS100DF410

www.ti.com.cn

ZHCS749B –JANUARY 2012–REVISED JANUARY 2015

Feature Description (continued)

7.3.7 CTLE Boost Setting

The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The

overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of

the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage

generally increases with increasing boost settings.

The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal.

Automatic adaptation of the CTLE only is the default mode of operation for the DS100DF410.

7.3.8 DFE Tap Weight and Polarity Setting

The DS100DF410 includes a five-tap decision-feedback equalizer (DFE) which operates on the signal at the

output of the CTLE.

When the tap weights and polarities are properly set, the DFE approximates a matched filter for the input

transmission channel frequency response as modified by the CTLE frequency response. The CTLE and the DFE

work together to compensate for the input transmission channel response.

The DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the

DS100DF410. When the DFE tap weights and polarities are properly set the DS100DF410 CDR operates at an

acceptable BER with more severe channel impairments than can be compensated with the CTLE alone.

It is possible to automatically or manually set the tap weights and polarities in the DS100DF410. Determining the

correct tap weights manually is difficult and time-consuming. The DS100DF410 automatically adapts the DFE tap

weights and polarities in normal operation. This automatic adaptation provides superior BER performance for

noisy channels and channels subject to crosstalk aggressors.

The DFE is powered down by default. In order for the DFE tap weights and polarities to be applied to the input

signal, bit 3 of register 0x1e, the dfe_PD bit, should be set to 0 to power up the DFE. Also the adapt mode

setting in register 0x31, bits[6:5] should be set to 2b'10 or 2b'11 so the device can automatically adapt the CTLE

and DFE.

7.3.9 Driver Output Voltage

The differential output voltage of the DS100DF410 can be configured from a nominal setting of 600 mV peak-to-

peak differential to a nominal setting of 1.3 V peak-to-peak differential, depending upon the application. The

driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.

7.3.10 Driver Output De-Emphasis

The output de-emphasis level of the DS100DF410 can be configured from a nominal setting of 0 dB to a nominal

setting of -12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide

more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output

driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for

greater dispersion in the transmission media at the output of the DS100DF410. The output de-emphasis level as

set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative

to the output VOD.

7.3.11 Driver Output Rise/Fall Time

In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic

interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory

compliance. In others, it can reduce the crosstalk in the system.

The DS100DF410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew

rate of the output drivers into the load capacitance. Alternatively, the DS100DF410 can be configured to operate

with a slightly greater rise/fall time if desired. For the typical specifications on rise/fall time, see Electrical

Characteristics.

DS100DF410

ZHCS749B –JANUARY 2012–REVISED JANUARY 2015

www.ti.com.cn

Feature Description (continued)

7.3.12 Ref_mode 0 Mode (Reference Clock Not Required)

The DS100DF410 can be used without using a reference clock and the input REFCLK_IN pin can be open.

When register 0x36, bits [5:4] are set to 2’b00, the device operates without using a reference clock at 10.3125

Gbps mode.

For 1GbE applications, it is required to bypass the CDR by setting the override bit 5 of register 0x09 to 1, and set

the data mux bits [7:5] to 3'b000 of register 0x1E.

7.3.13 Ref_mode 3 Mode (Reference Clock Required)

When using ref_mode 3, the device uses an external 25 MHz clock. This mode of operation is set in register

0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial

phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to

generate a 2.5V, 25 MHz reference signal which is connected to the DS100DF410 on the reference clock input

pin (pin 19). The DS100DF410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is

required.

The reference clock speeds up the initial phase lock acquisition. The DS100DF410 is set to phase lock to a

known data rate, or a constrained set of known data rates, and the digital circuitry in the DS100DF410 pre-

configures the VCO frequency. This enables the DS100DF410 phase-lock to the incoming signal very quickly.

The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous

to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The

retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS100DF410.

The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator can provide

an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that

only one reference oscillator is required in a system.

7.3.14 False Lock Detector Setting

The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to

enable the false lock detector function.

7.3.15 Reference Clock In

REFCLK_IN pin 19 is for reference clock input. A 25 MHz oscillator should be connected to pin 19. See Electrical

Characteristics for the requirements on the 25 MHz clock. The frequency of the reference clock should always be

25 MHz no matter what data rate or mode of operation is used.

7.3.16 Reference Clock Out

REFCLK_OUT pin 42 is the reference clock output pin. The DS100DF410 drives a buffered replica of the 25

MHz reference clock input on this output pin. If there are multiple DS100DF410 in the system, the REFCLK_OUT

pin can be directly connected to the REFCLK_IN pin of another DS100DF410 in a daisy chain connection. The

other option is to connect the external 25 MHz oscillator to a clock fanout buffer to distribute the 25 MHz clock to

each DS100DF410, which ensures there is a reference clock for the DS100DF410.

7.3.17 Daisy Chain of REFCLK_OUT to REFCLK_IN

When daisy chaining the device REFCLK_OUT to the REFCLK_IN of another device, the trace connection

should be less than 1.5 inches (about 5pF trace capacitance) and it is possible to cascade up to 9 devices. While

in other systems with longer interconnecting trace or more capacitive loading, the daisy chain of multiple devices

should be reduced. In a system which requires longer daisy chain, it is recommended to place an inverted gate

after the 6th devices. The pre-distorted duty cycle from the inverter allows longer daisy chain. A better approach

is to break the long daisy chain into shorter chains, each driven by a buffer version of the clock distribution and

with each chain kept to a maximum of 6 cascade devices. As an example, if there are 12 devices in the system,

the daisy chain connections can be divided into two groups of 6 devices and PCB trace length for the reference

clock output to input connection. Should be 1.5 inch or less.

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