0.25微米CMOS技术实现的高性能GHz频率合成器

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本文介绍了一种在标准0.25微米CMOS工艺中实现的吉赫兹级单片频率合成器。该设计实现了高性能无线通信和雷达系统所需的巨大频率覆盖范围，对于现代射频（RF）频率合成器而言具有重要意义。该频率合成器的主要特点是其低功耗和小型化设计。该器件仅消耗单个2.5伏电源的55毫瓦电力，这意味着它在节能方面具有显著的优势，特别适合电池供电或功率受限的应用。其高效能体现在全频率范围内都能提供稳定的功能，这对于需要宽频谱操作的设备来说是一个关键特性。最引人注目的是，输出信号的中心频率达到了2.25吉赫兹，而且具有出色的相位噪声性能，达到了-108分贝耦合噪声/赫兹（dBc/Hz）的水平。这在时钟和通信系统中是非常重要的，因为它能够提供更精确的频率参考和更低的噪声干扰，从而提升系统的整体性能和稳定性。此外，值得注意的是，这款单片频率合成器的封装尺寸仅为0.9毫米乘以0.9毫米，这在集成度和空间效率上达到了业界的领先水平，对于紧凑型设计的电子设备，如移动通信设备和物联网设备，这是一个巨大的优势。研究团队由三位来自国立台湾大学电气工程系的学者组成，他们共同开发了这一创新技术，展示了在现代CMOS技术下实现高性能、小型化频率合成器的可能性。他们的工作对于推动无线通信技术的发展，特别是对于那些对功耗、体积和性能要求苛刻的应用领域，有着显著的贡献。这篇论文为我们揭示了如何在当今的CMOS平台上构建高效能、低功耗的吉赫兹级频率合成器，它为无线通信设备的未来发展奠定了坚实的基础。

Gigahertz CMOS Monolithic Frequency Synthesizer

Rong-Jyi Yang

Department of Electrical Engineering

and Graduate Institute of Electronics

Engineering

National Taiwan University

Taipei, Taiwan 10617, R.O.C

886-2-23635251ext328

r0943049@ee.ntu.edu.tw

Ming-Zhe Liu

Department of Electrical Engineering

and Graduate Institute of Electronics

Engineering

National Taiwan University

Taipei, Taiwan 10617, R.O.C

886-2-23635251ext328

r9921003@ee.ntu.edu.tw

Shen-Iuan Liu

Department of Electrical Engineering

and Graduate Institute of Electronics

Engineering

National Taiwan University

Taipei, Taiwan 10617, R.O.C

886-2-23635251ext239

lsi@cc.ee.ntu.edu.tw

Abstract—In this paper, a gigahertz monolithic

frequency synthesizer was realized in a standard 0.25-

µµ

CMOS technology. It consumes 55 mW from a single 2.5-

V power supply, and is fully functional over the complete

frequency range of the interest. The output signal

spectrum of 2.25 GHz with the phase noise –108 dBc/Hz

at 0.5-MHz offset. Its die size is 0.9

✕✕

0.9 mm

. IntroductionⅠ

ⅠⅠ

Ⅰ

Today’s high-performance RF frequency synthesizers

are often required: (1) to operate over a wide frequency range

which can cover the required range; (2) to have smooth

transition among channel intervals; (3) to have small phase

jitter and frequency variation; and (4) to have an integrated

loop filter on the chip. Up to now, the frequency synthesizer

still is a major concern for monolithic integration.

In general, the PLL as shown in Figure 1 contains five

major building blocks, such as a VCO, a high frequency

divider (also called prescaler), a phase detector, a charge

pump and a low-pass filter. By varying the divide ratio of the

divider, the PLL can synthesize a new frequency based upon

the reference input while retaining the stability, accuracy, and

spectral purity of the original reference. Of course, the

addition of the fractional-N division technique can achieve

the narrow channel frequency spacing resolution. As shown

in Figure 1, the digital

Σ∆

-modulator generates a stream of

integers M(t) which can interpolate a fraction number

corresponding to the control input [1-3].

This divided signal is compared to the reference signal

in the phase detector, which gives output signals, U and D,

equal to the phase deference between its two inputs. Through

the charge pump circuit, the signals are low-pass filtered by

the loop filter, and are converted to be the control input to the

VCO. Under conditions of lock, the two inputs of the phase

detector have a constant phase relationship and thus equal

frequency. The output frequency therefore is (N+M)

⋅

REF.

Changing the frequency is done by changing the

divider modulus M(t), which result in an adjustable change of

the VCO control voltage as the loop acquires its steady-state

operating.

In the design of a PLL frequency synthesizer, the

specification of every component must be chosen with

extreme care. The VCO must be of high quality, the

frequency divider must have high speed, the phase detector

must be accurate, and the filter must provide an optimum

compromise in switching speed, frequency settling, output

noise, etc…

. Circuit DescriptionⅡ

ⅡⅡ

Ⅱ

2.1 Phase frequency detector

A common drawback for some phase detectors is a

dead zone in the phase characteristic at the equilibrium point.

The dead zone generates phase jitter since the control system

does not change the control voltage when the phase error is

within the dead zone [4].

A dynamic phase detector as shown in Figure 2(a) is

proposed in [5]. The proposed dynamic CMOS PFD is shown

in Figure 2(b), where the two PMOSFETs in the first stage

and the two NMOSFETs in the last stage have been

exchanged. Thereby the data line transistor is moved to the

middle, while the clock line transistor is moved to the power

rails.

The phase characteristics of the conventional PFDs and

dynamic PFDs are depicted in Figure 3. Unlike the

conventional PFD, there is less dead zone in the

characteristics of the dynamic PFDs. A magnification of the

characteristics at a zero phase is shown in Figure 3. All data

are based on simulation with 0.25-

m CMOS model when

supply voltage of 2.5V and operating frequency of 10MHz.

Furthermore, the dynamic CMOS PFD has a better

property in dead zone effect than the conventional PFD. It

can be explained in the following. When the PLL is near

locked, if the signal R lags the signal V, there is a very small

output signal to denote their phase difference. Just after the

output of D is active, the input signal R changes to low and

make MN

off and MP

on as shown in Figure 2.

Simultaneously, the voltages of C

, C

and C

, C

are

equal to supply value. Then the reset path will reactivate

through the NAND gate since U has changed to high; it can

turn on MP

and MP

, then indirectly turn on MN

and

. However, when MN

is turned on, it should

discharge the charge stored on C

and C

since MP

had

been on, resulting in the reset speed slow. In the right hand of

232

2002 VLSI/CAD, Taiwan

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