ADUC812技术手册：12位嵌入式闪存MCU详解

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ADUC812是一款由Analog Devices公司生产的MicroConverter™多通道12位逐次逼近型ADC（Analog-to-Digital Converter），集成了嵌入式Flash MCU（微控制器）功能。该设备设计用于实现高精度数据转换，具有8051兼容的微控制器核心，支持多种功能块，包括电源管理、监控、看门狗定时器、2-wire串行接口、闪存数据存储以及丰富的RAM和DAC（数字模拟转换器）。产品特点如下： 1. **内部结构**：该设备具有一个完整的系统架构，包括微控制器模块、电源供应单元、温度传感器、模拟输入缓冲器、12位ADC、双通道DAC（DAC0和DAC1）、串行通信接口（如SPI和2-wire I/O）以及数据存储区（640字节的Flash和EEPROM，以及256字节的用户RAM）。 2. **ADC部分**：12位的ADC具有高精度，可用于采集各种模拟信号，并通过内置的控制和校准逻辑进行精确转换。它还配备了模数转换器缓冲器，确保信号传输的稳定性和可靠性。 3. **微控制器功能**：作为一个8051兼容的微控制器，它支持中断处理、定时器（T0, T1, T2）和扩展定时器（T2EX），以及基本输入/输出（Pins P3.0-P3.5），如ALE、PSEN、EA和复位信号（RESE）。 4. **通信接口**：设备提供了2线串行接口，便于与外部设备通信，包括RXD（P3.1）和TXD（P3.0）数据线，以及SCLOCK时钟信号。 5. **电源管理**：除了主电源（DVDD）和模拟地（AGND），还有AVDD和电压参考（2.5V REF）接口，确保了设备在不同工作环境下的稳定供电。 6. **外设接口**：包括MOSI/SDATA（P3.3）作为数字输出，MISO（P3.3）作为数字输入，以及XTAL1和XTAL2用于系统时钟的外部晶体振荡器。 ADUC812手册对于不同层次的学习者都很有价值，无论是初学者了解其硬件配置，还是高级工程师进行系统集成和优化，都能从中找到所需的信息。由于其丰富的特性及高度集成，这款芯片适用于工业控制、信号处理、测量和传感应用等多种领域。在使用前，请务必注意版权声明和责任免责声明，确保合法使用并尊重知识产权。

REV. 0

ADuC812

–6–

PIN FUNCTION DESCRIPTIONS

Mnemonic Type Function

P Digital Positive Supply Voltage, +3 V or +5 V nominal.

P Analog Positive Supply Voltage, +3 V or +5 V nominal.

REF

I Decoupling pin for on-chip reference. Connect 0.1 µF between this pin and AGND.

REF

I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the

reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this

appears at the pin (once the ADC or DAC peripherals are enabled). This pin can be overdriven by an exter-

nal reference.

AGND G Analog Ground. Ground Reference point for the analog circuitry.

P1.0–P1.7 I Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure

any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share

the following functionality.

ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.

T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to

a 1 to 0 transition of the T2 input.

T2EX I Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for

Counter 2.

SS I Slave Select input for the SPI interface.

SDATA I/O User selectable, I

C-Compatible Input/Output pin or SPI Data Input/Output pin.

SCLOCK I/O Serial Clock pin for I

C-Compatible or SPI serial interface clock.

MOSI I/O SPI Master Output/Slave Input Data I/O pin for SPI interface.

MISO I/O Master Input/Slave Output Data I/O pin for SPI Serial Interface.

DAC0 O Voltage Output from DAC0.

DAC1 O Voltage Output from DAC1.

RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the

device.

P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are

pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3

pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also

contain various secondary functions which are described below.

RxD I/O Receiver Data Input (asynchronous) or Data Input/ Output (synchronous) of serial (UART) port.

TxD O Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.

INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two

priority levels. This pin can also be used as a gate control input to Timer 0.

INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two

priority levels. This pin can also be used as a gate control input to Timer 1.

T0 I Timer/Counter 0 Input.

T1 I Timer/Counter 1 Input.

CONVST I Active low Convert Start Logic input for the ADC block when the external Convert start function is en-

abled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.

WR O Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.

RD O Read Control Signal, Logic Output. Enables the external data memory to Port 0.

XTAL2 O Output of the inverting oscillator amplifier.

XTAL1 I Input to the inverting oscillator amplifier and input to the internal clock generator circuits.

DGND G Digital Ground. Ground reference point for the digital circuitry.

P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are

(A8–A15) pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2

(A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits

the high order address bytes during fetches from external program memory and middle and high order

address bytes during accesses to the external 24-bit external data memory space.

PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program

memory to the bus during external fetch operations. It is active every six oscillator periods except during

external data memory accesses. This pin remains high during internal program execution. PSEN can also be

used to enable serial download mode when pulled low through a resistor on power-up or RESET.

REV. 0

ADuC812

–7–

Mnemonic Type Function

ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and middle byte for 24-bit

address space accesses) of the address into external memory during normal operation. It is activated every

six oscillator periods except during an external data memory access.

EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from

internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch

all instructions from external program memory.

P0.7–P0.0 I/O Port 0 is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in that

(A0–A7) state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus

during accesses to external program or data memory. In this application it uses strong internal pull-ups

when emitting 1s.

TERMINOLOGY

ADC SPECIFICATIONS

Integral Nonlinearity

This is the maximum deviation of any code from a straight line

passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale, a point

1/2 LSB below the first code transition and full scale, a point

1/2 LSB above the last code transition.

Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Offset Error

This is the deviation of the first code transition (0000 . . . 000)

to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.

Full-Scale Error

This is the deviation of the last code transition from the ideal

AIN voltage (Full Scale – 1.5 LSB) after the offset error has

been adjusted out.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the rms sum of all nonfundamental

signals up to half the sampling frequency (f

/2), excluding dc.

The ratio is dependent upon the number of quantization levels

in the digitization process; the more levels, the smaller the quan-

tization noise. The theoretical signal to (noise +distortion) ratio

for an ideal N-bit converter with a sine wave input is given by:

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Total Harmonic Distortion is the ratio of the rms sum of the

harmonics to the fundamental.

DAC SPECIFICATIONS

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maxi-

mum deviation from a straight line passing through the end-

points of the DAC transfer function. It is measured after

adjusting for zero error and full-scale error.

Voltage Output Settling Time

This is the amount of time it takes for the output to settle to a

specified level for a full-scale input change.

Digital to Analog Glitch Impulse

This is the amount of charge injected into the analog output

when the inputs change state. It is specified as the area of the

glitch in nV sec.

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