TM4C123G微控制器详尽文档：应用实例与全面指南

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本文档详尽介绍了TI Tiva TM4C123GH6PMMicrocontroller，它与LM4F230H5QR型号相同，是专为嵌入式系统设计的一款高性能微控制器。该文档长达一千多页，覆盖了广泛的硬件、软件以及应用案例，旨在帮助开发人员全面理解和利用这款设备的各种特性。文档的核心内容包括： 1. **产品概述**： TM4C123GH6PM提供了ARM Cortex-M4F架构，具有丰富的外围接口如ADC、DAC、CAN、SPI、I2C、USART等，支持低功耗模式和高速处理能力，适合工业控制、物联网、无线通信等领域。 2. **规格参数**： - CPU性能：Cortex-M4F，工作频率高达168MHz，具有浮点运算单元(FPU)和1MB闪存和512KB SRAM。 - 电源管理：支持多种省电模式，满足电池供电设备的需求。 - 时钟和外设接口：提供多种可配置的时钟源和外设接口选项。 3. **功能描述**： - 详细解释了数字信号处理器(DSP)特性和中断管理，以及内存管理和存储结构。 - 指明了片上外设的驱动和控制方法，包括GPIO、定时器、计数器、看门狗等。 4. **编程接口**：提供了丰富的API和SDK支持，如CCS（Code Composer Studio）、Keil uVision等开发工具，以及适用于不同操作系统（如RTOS）的示例代码。 5. **应用实例**：文档中包含了一系列实际项目中的应用案例，展示了如何使用TM4C123GH6PM进行电机控制、传感器数据处理、无线通信等任务。 6. **生产信息与警告**：附带了关于产品可用性、标准保修政策以及在关键应用中的使用限制和免责声明。总结来说，这份TM4C123GH6PM微控制器详细文档是一份宝贵的资源，对于希望开发基于此芯片的项目工程师而言，无论是初学者还是经验丰富的开发人员，都能从中找到所需的设计指导、技术细节和最佳实践。通过阅读和理解这份文档，用户能够确保其产品设计符合性能要求，并充分发掘TM4C123GH6PM的潜力。

Table 16-2. Examples of I

C Master Timer Period versus Speed Mode ................................... 999

Table 16-3. Examples of I

C Master Timer Period in High-Speed Mode ................................ 1000

Table 16-4. Inter-Integrated Circuit (I

C) Interface Register Map ........................................... 1012

Table 16-5. Write Field Decoding for I2CMCS[3:0] Field ....................................................... 1018

Table 17-1. Controller Area Network Signals (64LQFP) ........................................................ 1045

Table 17-2. Message Object Configurations ........................................................................ 1050

Table 17-3. CAN Protocol Ranges ...................................................................................... 1058

Table 17-4. CANBIT Register Values .................................................................................. 1058

Table 17-5. CAN Register Map ........................................................................................... 1062

Table 18-1. USB Signals (64LQFP) .................................................................................... 1096

Table 18-2. Remainder (MAXLOAD/4) ................................................................................ 1107

Table 18-3. Actual Bytes Read ........................................................................................... 1107

Table 18-4. Packet Sizes That Clear RXRDY ...................................................................... 1108

Table 18-5. Universal Serial Bus (USB) Controller Register Map ........................................... 1109

Table 19-1. Analog Comparators Signals (64LQFP) ............................................................. 1210

Table 19-2. Internal Reference Voltage and ACREFCTL Field Values ................................... 1212

Table 19-3. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1213

Table 19-4. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1213

Table 19-5. Analog Comparators Register Map ................................................................... 1214

Table 20-1. PWM Signals (64LQFP) ................................................................................... 1227

Table 20-2. PWM Register Map .......................................................................................... 1234

Table 21-1. QEI Signals (64LQFP) ...................................................................................... 1301

Table 21-2. QEI Register Map ............................................................................................ 1305

Table 23-1. GPIO Pins With Default Alternate Functions ...................................................... 1323

Table 23-2. Signals by Pin Number ..................................................................................... 1324

Table 23-3. Signals by Signal Name ................................................................................... 1331

Table 23-4. Signals by Function, Except for GPIO ............................................................... 1337

Table 23-5. GPIO Pins and Alternate Functions ................................................................... 1344

Table 23-6. Possible Pin Assignments for Alternate Functions .............................................. 1346

Table 23-7. Connections for Unused Signals (64-Pin LQFP) ................................................. 1349

Table 24-1. Maximum Ratings ............................................................................................ 1351

Table 24-2. ESD Absolute Maximum Ratings ...................................................................... 1351

Table 24-3. Temperature Characteristics ............................................................................. 1352

Table 24-4. Thermal Characteristics ................................................................................... 1352

Table 24-5. Recommended DC Operating Conditions .......................................................... 1353

Table 24-6. Recommended GPIO Pad Operating Conditions ................................................ 1353

Table 24-7. GPIO Current Restrictions ................................................................................ 1353

Table 24-8. GPIO Package Side Assignments ..................................................................... 1354

Table 24-9. JTAG Characteristics ....................................................................................... 1356

Table 24-10. Power-On and Brown-Out Levels ...................................................................... 1358

Table 24-11. Reset Characteristics ....................................................................................... 1363

Table 24-12. LDO Regulator Characteristics ......................................................................... 1365

Table 24-13. Phase Locked Loop (PLL) Characteristics ......................................................... 1366

Table 24-14. Actual PLL Frequency ...................................................................................... 1366

Table 24-15. PIOSC Clock Characteristics ............................................................................ 1367

Table 24-16. Low-Frequency internal Oscillator Characteristics .............................................. 1367

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Table of Contents

Table 24-17. Hibernation Oscillator Input Characteristics ........................................................ 1367

Table 24-18. Main Oscillator Input Characteristics ................................................................. 1368

Table 24-19. Crystal Parameters .......................................................................................... 1369

Table 24-20. Supported MOSC Crystal Frequencies .............................................................. 1370

Table 24-21. System Clock Characteristics with ADC Operation ............................................. 1371

Table 24-22. System Clock Characteristics with USB Operation ............................................. 1371

Table 24-23. Sleep Modes AC Characteristics ....................................................................... 1372

Table 24-24. Time to Wake with Respect to Low-Power Modes .............................................. 1372

Table 24-25. Hibernation Module Battery Characteristics ....................................................... 1374

Table 24-26. Hibernation Module AC Characteristics ............................................................. 1374

Table 24-27. Flash Memory Characteristics ........................................................................... 1375

Table 24-28. EEPROM Characteristics ................................................................................. 1375

Table 24-29. GPIO Module Characteristics ............................................................................ 1376

Table 24-30. Pad Voltage/Current Characteristics for Fail-Safe Pins ....................................... 1377

Table 24-31. Fail-Safe GPIOs that Require an External Pull-up .............................................. 1378

Table 24-32. Non-Fail-Safe I/O Pad Voltage/Current Characteristics ....................................... 1378

Table 24-33. ADC Electrical Characteristics .......................................................................... 1380

Table 24-34. SSI Characteristics .......................................................................................... 1383

Table 24-35. I

C Characteristics ........................................................................................... 1386

Table 24-36. Analog Comparator Characteristics ................................................................... 1388

Table 24-37. Analog Comparator Voltage Reference Characteristics ...................................... 1388

Table 24-38. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 0 .......................................................................................................... 1388

Table 24-39. Analog Comparator Voltage Reference Characteristics, V

DDA

= 3.3V, EN= 1, and

RNG = 1 .......................................................................................................... 1389

Table 24-40. Current Consumption ....................................................................................... 1390

Table A-1. Orderable Part Numbers .................................................................................. 1393

17July 17, 2013

Texas Instruments-Production Data

Tiva

™

TM4C123GH6PM Microcontroller

(identical to LM4F230H5QR)

List of Registers

The Cortex-M4F Processor ........................................................................................................... 67

Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 75

Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 75

Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 75

Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 75

Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 75

Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 75

Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 75

Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 75

Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 75

Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 75

Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 75

Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 75

Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 75

Register 14: Stack Pointer (SP) ........................................................................................................... 76

Register 15: Link Register (LR) ............................................................................................................ 77

Register 16: Program Counter (PC) ..................................................................................................... 78

Register 17: Program Status Register (PSR) ........................................................................................ 79

Register 18: Priority Mask Register (PRIMASK) .................................................................................... 83

Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 84

Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 85

Register 21: Control Register (CONTROL) ........................................................................................... 86

Register 22: Floating-Point Status Control (FPSC) ................................................................................ 88

Cortex-M4 Peripherals ................................................................................................................. 120

Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 140

Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104 ................................................................ 140

Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108 ................................................................ 140

Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C ............................................................. 140

Register 8: Interrupt 128-138 Set Enable (EN4), offset 0x110 ............................................................ 141

Register 9: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 142

Register 10: Interrupt 32-63 Clear Enable (DIS1), offset 0x184 ............................................................ 142

Register 11: Interrupt 64-95 Clear Enable (DIS2), offset 0x188 ............................................................ 142

Register 12: Interrupt 96-127 Clear Enable (DIS3), offset 0x18C .......................................................... 142

Register 13: Interrupt 128-138 Clear Enable (DIS4), offset 0x190 ........................................................ 143

Register 14: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 144

Register 15: Interrupt 32-63 Set Pending (PEND1), offset 0x204 ......................................................... 144

Register 16: Interrupt 64-95 Set Pending (PEND2), offset 0x208 ......................................................... 144

Register 17: Interrupt 96-127 Set Pending (PEND3), offset 0x20C ....................................................... 144

Register 18: Interrupt 128-138 Set Pending (PEND4), offset 0x210 ...................................................... 145

Register 19: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 146

Register 20: Interrupt 32-63 Clear Pending (UNPEND1), offset 0x284 .................................................. 146

Register 21: Interrupt 64-95 Clear Pending (UNPEND2), offset 0x288 .................................................. 146

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Texas Instruments-Production Data

Table of Contents

Register 24: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 148

Register 25: Interrupt 32-63 Active Bit (ACTIVE1), offset 0x304 ........................................................... 148

Register 26: Interrupt 64-95 Active Bit (ACTIVE2), offset 0x308 ........................................................... 148

Register 27: Interrupt 96-127 Active Bit (ACTIVE3), offset 0x30C ........................................................ 148

Register 28: Interrupt 128-138 Active Bit (ACTIVE4), offset 0x310 ....................................................... 149

Register 29: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 150

Register 30: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 150

Register 31: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 150

Register 32: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 150

Register 33: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 150

Register 34: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 150

Register 35: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 150

Register 36: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 150

Register 37: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 150

Register 38: Interrupt 36-39 Priority (PRI9), offset 0x424 ..................................................................... 150

Register 39: Interrupt 40-43 Priority (PRI10), offset 0x428 ................................................................... 150

Register 40: Interrupt 44-47 Priority (PRI11), offset 0x42C ................................................................... 150

Register 41: Interrupt 48-51 Priority (PRI12), offset 0x430 ................................................................... 150

Register 42: Interrupt 52-55 Priority (PRI13), offset 0x434 ................................................................... 150

Register 43: Interrupt 56-59 Priority (PRI14), offset 0x438 ................................................................... 150

Register 44: Interrupt 60-63 Priority (PRI15), offset 0x43C .................................................................. 150

Register 45: Interrupt 64-67 Priority (PRI16), offset 0x440 ................................................................... 152

Register 46: Interrupt 68-71 Priority (PRI17), offset 0x444 ................................................................... 152

Register 47: Interrupt 72-75 Priority (PRI18), offset 0x448 ................................................................... 152

Register 48: Interrupt 76-79 Priority (PRI19), offset 0x44C .................................................................. 152

Register 49: Interrupt 80-83 Priority (PRI20), offset 0x450 ................................................................... 152

Register 50: Interrupt 84-87 Priority (PRI21), offset 0x454 ................................................................... 152

Register 51: Interrupt 88-91 Priority (PRI22), offset 0x458 ................................................................... 152

Register 52: Interrupt 92-95 Priority (PRI23), offset 0x45C .................................................................. 152

Register 53: Interrupt 96-99 Priority (PRI24), offset 0x460 ................................................................... 152

Register 54: Interrupt 100-103 Priority (PRI25), offset 0x464 ............................................................... 152

Register 55: Interrupt 104-107 Priority (PRI26), offset 0x468 ............................................................... 152

Register 56: Interrupt 108-111 Priority (PRI27), offset 0x46C ............................................................... 152

Register 57: Interrupt 112-115 Priority (PRI28), offset 0x470 ................................................................ 152

Register 58: Interrupt 116-119 Priority (PRI29), offset 0x474 ................................................................ 152

Register 59: Interrupt 120-123 Priority (PRI30), offset 0x478 ............................................................... 152

Register 60: Interrupt 124-127 Priority (PRI31), offset 0x47C ............................................................... 152

Register 61: Interrupt 128-131 Priority (PRI32), offset 0x480 ............................................................... 152

Register 62: Interrupt 132-135 Priority (PRI33), offset 0x484 ............................................................... 152

Register 63: Interrupt 136-138 Priority (PRI34), offset 0x488 ............................................................... 152

Register 64: Software Trigger Interrupt (SWTRIG), offset 0xF00 .......................................................... 154

Register 65: Auxiliary Control (ACTLR), offset 0x008 .......................................................................... 155

Register 66: CPU ID Base (CPUID), offset 0xD00 ............................................................................... 157

Register 67: Interrupt Control and State (INTCTRL), offset 0xD04 ........................................................ 158

Register 68: Vector Table Offset (VTABLE), offset 0xD08 .................................................................... 161

19July 17, 2013

Texas Instruments-Production Data

Tiva

™

TM4C123GH6PM Microcontroller

(identical to LM4F230H5QR)

Register 70: System Control (SYSCTRL), offset 0xD10 ....................................................................... 164

Register 71: Configuration and Control (CFGCTRL), offset 0xD14 ....................................................... 166

Register 72: System Handler Priority 1 (SYSPRI1), offset 0xD18 ......................................................... 168

Register 73: System Handler Priority 2 (SYSPRI2), offset 0xD1C ........................................................ 169

Register 74: System Handler Priority 3 (SYSPRI3), offset 0xD20 ......................................................... 170

Register 76: Configurable Fault Status (FAULTSTAT), offset 0xD28 ..................................................... 175

Register 77: Hard Fault Status (HFAULTSTAT), offset 0xD2C .............................................................. 181

Register 79: Bus Fault Address (FAULTADDR), offset 0xD38 .............................................................. 183

Register 80: MPU Type (MPUTYPE), offset 0xD90 ............................................................................. 184

Register 81: MPU Control (MPUCTRL), offset 0xD94 .......................................................................... 185

Register 91: Coprocessor Access Control (CPAC), offset 0xD88 .......................................................... 193

Register 92: Floating-Point Context Control (FPCC), offset 0xF34 ........................................................ 194

Register 93: Floating-Point Context Address (FPCA), offset 0xF38 ...................................................... 196

System Control ............................................................................................................................ 210

Register 1: Device Identification 0 (DID0), offset 0x000 ..................................................................... 236

Register 2: Device Identification 1 (DID1), offset 0x004 ..................................................................... 238

Register 4: Raw Interrupt Status (RIS), offset 0x050 .......................................................................... 242

Register 5: Interrupt Mask Control (IMC), offset 0x054 ...................................................................... 245

Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................. 247

Register 7: Reset Cause (RESC), offset 0x05C ................................................................................ 250

Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 ......................................................... 252

Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 .................................................... 258

Register 11: Main Oscillator Control (MOSCCTL), offset 0x07C ........................................................... 261

Register 13: System Properties (SYSPROP), offset 0x14C .................................................................. 264

Register 16: PLL Frequency 0 (PLLFREQ0), offset 0x160 ................................................................... 269

Register 17: PLL Frequency 1 (PLLFREQ1), offset 0x164 ................................................................... 270

Register 18: PLL Status (PLLSTAT), offset 0x168 ............................................................................... 271

July 17, 201320

Texas Instruments-Production Data

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