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JEDEC Standard No. 209-4D
Figures
Figure 1 — Dual channel die ........................................................................................................................2
Figure 2 — Single channel die .....................................................................................................................3
Figure 3 — Two Byte mode die configuration ..............................................................................................4
Figure 4 — Mixed package configuration example ....................................................................................23
Figure 5 — ZQ Wiring Overview.................................................................................................................24
Figure 6 — LPDDR4:Simplified Bus Interface State Diagram - Sheet 1 ....................................................36
Figure 7 — LPDDR4:Simplified Bus Interface State Diagram - Sheet 2 ....................................................37
Figure 8 — Power Ramp and Initialization Sequence ................................................................................39
Figure 9 — Dual channel die configuration example..................................................................................68
Figure 10 — ACTIVATE Command............................................................................................................77
Figure 11 — tFAW Timing ..........................................................................................................................78
Figure 12 — DQS Read Preamble and Postamble: Toggling Preamble and 0.5nCK Postamble..............81
Figure 13 — DQS Read Preamble and Postamble: Static Preamble and 1.5nCK Postamble...................81
Figure 14 — Burst Read Timing .................................................................................................................83
Figure 15 — Burst Read followed by Burst Write or Burst Mask Write ......................................................84
Figure 16 — Seamless Burst Read ............................................................................................................85
Figure 17 — Read Timing ..........................................................................................................................86
Figure 18 — tLZ(DQS) method for calculating transitions and end point ...................................................87
Figure 19 — tHZ(DQS) method for calculating transitions and end point ..................................................88
Figure 20 — tLZ(DQ) method for calculating transitions and end point .....................................................89
Figure 21 — tHZ(DQ) method for calculating transitions and end point.....................................................90
Figure 22 — Method for calculating tRPRE transitions and endpoints.......................................................91
Figure 23 — Method for calculating tRPRE transitions and endpoints.......................................................91
Figure 24 — Method for calculating tRPST transitions and endpoints .......................................................92
Figure 25 — DQS Write Preamble and Postamble: 0.5nCK Postamble ....................................................94
Figure 26 — DQS Write Preamble and Postamble: 1.5nCK Postamble ....................................................95
Figure 27 — Burst Write Operation ............................................................................................................96
Figure 28 — Burst Write Followed by Burst Read......................................................................................97
Figure 29 — Write Timing...........................................................................................................................98
Figure 30 — Method for calculating tWPRE transitions and endpoints......................................................99
Figure 31 — Method for calculating tWPST transitions and endpoints ....................................................100
Figure 32 — WDQS Control Mode 1 - Read Based Control ....................................................................103
Figure 33 — Burst Write Operation ..........................................................................................................105
Figure 34 — Burst Read followed by Burst Write or Burst Mask Write (ODT Disable) ............................105
Figure 35 — Burst Read followed by Burst Write or Burst Mask Write (ODT Enable) ............................. 106
Figure 36 — Seamless Reads Operation: tCCD = Min, Preamble = Toggle, 1.5nCK Postamble............107
Figure 37 — Consecutive Reads Operation: tCCD = Min +1, Preamble = Toggle, 1.5nCK Postamble... 108
Figure 38 — Consecutive Reads Operation: tCCD = Min +1, Preamble = Toggle, 0.5nCK Postamble... 109
Figure 39 — Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 1.5nCK Postamble.....110
Figure 40 — Consecutive Reads Operation: tCCD = Min +1, Preamble = Static, 0.5nCK Postamble.....111
Figure 41 — Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 1.5nCK Postamble... 112
Figure 42 — Consecutive Reads Operation: tCCD = Min +2, Preamble = Toggle, 0.5nCK Postamble... 113
Figure 43 — Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 1.5nCK Postamble.....114
Figure 44 — Consecutive Reads Operation: tCCD = Min +2, Preamble = Static, 0.5nCK Postamble.....115
Figure 45 — Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 1.5nCK Postamble... 116
Figure 46 — Consecutive Reads Operation: tCCD = Min +3, Preamble = Toggle, 0.5nCK Postamble... 117
Figure 47 — Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 1.5nCK Postamble.....118
Figure 48 — Consecutive Reads Operation: tCCD = Min +3, Preamble = Static, 0.5nCK Postamble.....119
Figure 49 — Seamless Writes Operation: tCCD = Min, 0.5nCK Postamble ............................................120
Figure 50 — Seamless Writes Operation: tCCD = Min, 1.5nCK Postamble, 533MHz < Clock Freq. £
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