![](https://csdnimg.cn/release/download_crawler_static/10371653/bg13.jpg)
IEEE
UNIFIED HARDWARE DESIGN, SPECIFICATION, AND VERIFICATION LANGUAGE Std 1800-2005
Copyright © 2005 IEEE. All rights reserved.
3
— Race-free program context
— Assertion mechanism for verifying design intent and functional coverage intent
— Property and sequence declarations
— Assertions and coverage statements with action blocks
— Extended hierarchy support
— Packages for declaration encapsulation with import for controlled access
— Compilation-unit scope nested modules and extern modules for separate compilation support
— Extension of port declarations to support interfaces, events, and variables
— $root to provide unambiguous access using hierarchical references
— Interfaces to encapsulate communication and facilitate communication-oriented design
— Functional coverage
— DPI for clean, efficient interoperation with other languages (C provided)
— Assertion API
— Coverage API
— Data read API
— Verilog procedural interface (VPI) extensions for SystemVerilog constructs
— Concurrent assertion formal semantics
1.3 Conventions used in this standard
This standard is organized into clauses, each of which focuses on a specific area of the language. There are
subclauses within each clause to discuss individual constructs and concepts. The discussion begins with an
introduction and an optional rationale for the construct or the concept, followed by syntax and semantic
descriptions, followed by examples and notes.
The terminology conventions used throughout this standard are as follows:
— The word shall is used to indicate mandatory requirements strictly to be followed in order to con-
form to the standard and from which no deviation is permitted (shall equals is required to).
— The word should is used to indicate that among several possibilities one is recommended as particu-
larly suitable, without mentioning or excluding others; or that a certain course of action is preferred
but not necessarily required; or that (in the negative form) a certain course of action is deprecated
but not prohibited (should equals is recommended that).
— The word may is used to indicate a course of action permissible within the limits of the standard
(may equals is permitted to).
— The word can is used for statements of possibility and capability, whether material, physical, or
causal (can equals is able to).
1.4 Syntactic description
The main text uses the following conventions:
— Italicized font when a term is being defined
—
Constant-width font for examples, file names, and references to constants, especially 0, 1, x, and
z values
—
Boldface constant-width font for Verilog and SystemVerilog keywords, when referring to the
actual keyword
Authorized licensed use limited to: Akademia Gorniczo-Hutnicza. Downloaded on February 06,2012 at 14:55:20 UTC from IEEE Xplore. Restrictions apply.