SystemVerilog IEEE Std 1800-2005：硬件设计与验证的统一语言标准

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IEEE Std 1800-2005，全称为《系统Verilog统一硬件设计、规格说明与验证语言标准》，是电子和电气工程师学会（IEEE）发布的一项重要规范，旨在为硬件设计、验证过程提供一个标准化的、功能强大的语言。该标准于2005年11月22日正式发布，由设计自动化标准委员会（Design Automation Standards Committee）和IEEE标准化协会企业咨询组共同赞助。 SystemVerilog是一种广泛应用于电子系统设计的高级硬件描述语言，它结合了先前的Verilog和VHDL的优点，提供了一种统一的框架，支持设计者在从概念设计到实现的整个生命周期中进行高效的系统级描述。该标准包括了一系列关键特性，如模块化编程、并发性和数据流操作，使得设计者能够编写出可读性好、复用性强的代码，便于团队协作和维护。标准涵盖了系统级设计的各个方面，包括行为模型、组合逻辑、时序逻辑、接口描述、并发处理、并发数据流、随机测试和覆盖分析等。它还定义了语法、语义、仿真和验证规则，确保了不同工具间的设计兼容性和一致性。SystemVerilog允许设计者进行高级抽象，同时保持底层实现的灵活性，这对于现代SoC（系统级芯片）和FPGA（现场可编程门阵列）的设计尤为重要。 IEEE Std 1800-2005的版权属于IEEE，所有权利受法律保护。标准的发布不仅限于学术界，但下载时可能受到限制，例如，Academia Gorniczo-Hutnicza在2012年2月6日的下载即受到相关规定约束。此外，该标准的印刷版和光盘版均有特定的国际标准书号（ISBN）。 SystemVerilog作为一种重要的硬件描述语言标准，为电子设计工程师提供了强大的工具，提升了设计效率和质量，对于电子系统的设计、验证和一致性管理具有深远影响。随着技术的发展，该标准可能会随着时间而更新和完善，以适应不断变化的硬件设计需求。

28.4 Control functions ................................................................................................................. 471

29. SystemVerilog code coverage control and API ............................................................................... 473

29.1 Requirements ....................................................................................................................... 473

29.2 SystemVerilog real-time coverage access ........................................................................... 473

29.3 FSM recognition .................................................................................................................. 478

29.4 VPI coverage extensions...................................................................................................... 481

30. SystemVerilog data read API .......................................................................................................... 485

30.1 Introduction.......................................................................................................................... 485

30.2 Requirements ....................................................................................................................... 485

30.3 Extensions to VPI enumerations.......................................................................................... 486

30.4 VPI object type additions..................................................................................................... 487

30.5 Object model diagrams ........................................................................................................ 489

30.6 Usage extensions to VPI routines ........................................................................................ 489

30.7 VPI routines added in SystemVerilog ................................................................................. 492

30.8 Reading data ........................................................................................................................ 493

30.9 Optionally unloading data.................................................................................................... 503

30.10 Reading data from multiple databases and/or different read library providers ................... 503

30.11 VPI routines extended in SystemVerilog............................................................................. 506

30.12 VPI routines added in SystemVerilog ................................................................................. 507

Annex A (normative) Formal syntax ........................................................................................................... 511

Annex B (normative) Keywords.................................................................................................................. 551

Annex C (normative) Std package............................................................................................................... 553

Annex D (normative) Linked lists ............................................................................................................... 555

Annex E (normative) Formal semantics of concurrent assertions............................................................... 563

Annex F (normative) DPI C layer................................................................................................................ 575

Annex G (normative) Include file svdpi.h ................................................................................................... 607

Annex H (normative) Inclusion of foreign language code ..........................................................................617

Annex I (normative) sv_vpi_user.h ............................................................................................................. 621

Annex J (informative) Glossary................................................................................................................... 631

Annex K (informative) Bibliography .......................................................................................................... 635

Index ........................................................................................................................................................... 637

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IEEE

Std 1800-2005 IEEE STANDARD FOR S

YSTEMVERILOG:

SystemVerilog adds extended and new constructs to Verilog, including the following:

— Extensions to data types for better encapsulation and compactness of code and for tighter

specification

— C data types:

int, typedef, struct, union, enum

— Other data types: bounded queues, logic (0, 1, X, Z) and bit (0, 1), tagged unions for safety

— Dynamic data types: string, classes, dynamic queues, dynamic arrays, associative arrays

including automatic memory management freeing users from deallocation issues

— Dynamic casting and bit-stream casting

— Automatic/static specification on a per-variable-instance basis

— Extended operators for concise description

— Wild equality and inequality

— Built-in methods to extend the language

— Operator overloading

— Streaming operators

— Set membership

— Extended procedural statements

— Pattern matching on selection statements for use with tagged unions

— Enhanced loop statements plus the foreach statement

— C-like jump statements: return, break, continue

—

final blocks that execute at the end of simulation (inverse of initial)

— Extended event control and sequence events

— Enhanced process control

— Extensions to

always blocks to include synthesis consistent simulation semantics

— Extensions to

fork…join to model pipelines and for enhanced process control

— Fine-grain process control

— Enhanced tasks and functions

— C-like void functions

— Pass by reference

— Default arguments

— Argument binding by name

— Optional arguments

— Import/export functions for DPI

— Classes: object-oriented mechanism that provides abstraction, encapsulation, and safe pointer

capabilities

— Automated testbench support with random constraints

— Interprocess communication synchronization

— Semaphores

— Mailboxes

— Event extensions, event variables, and event sequencing

— Clarification and extension of the scheduling semantics

— Cycle-based functionality:

clocking blocks and cycle-based attributes that help reduce develop-

ment, ease maintainability, and promote reusability

— Cycle-based signal drives and samples

— Synchronous samples

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IEEE

UNIFIED HARDWARE DESIGN, SPECIFICATION, AND VERIFICATION LANGUAGE Std 1800-2005

— Race-free program context

— Assertion mechanism for verifying design intent and functional coverage intent

— Property and sequence declarations

— Assertions and coverage statements with action blocks

— Extended hierarchy support

— Packages for declaration encapsulation with import for controlled access

— Compilation-unit scope nested modules and extern modules for separate compilation support

— Extension of port declarations to support interfaces, events, and variables

— $root to provide unambiguous access using hierarchical references

— Interfaces to encapsulate communication and facilitate communication-oriented design

— Functional coverage

— DPI for clean, efficient interoperation with other languages (C provided)

— Assertion API

— Coverage API

— Data read API

— Verilog procedural interface (VPI) extensions for SystemVerilog constructs

— Concurrent assertion formal semantics

1.3 Conventions used in this standard

This standard is organized into clauses, each of which focuses on a specific area of the language. There are

subclauses within each clause to discuss individual constructs and concepts. The discussion begins with an

introduction and an optional rationale for the construct or the concept, followed by syntax and semantic

descriptions, followed by examples and notes.

The terminology conventions used throughout this standard are as follows:

— The word shall is used to indicate mandatory requirements strictly to be followed in order to con-

form to the standard and from which no deviation is permitted (shall equals is required to).

— The word should is used to indicate that among several possibilities one is recommended as particu-

larly suitable, without mentioning or excluding others; or that a certain course of action is preferred

but not necessarily required; or that (in the negative form) a certain course of action is deprecated

but not prohibited (should equals is recommended that).

— The word may is used to indicate a course of action permissible within the limits of the standard

(may equals is permitted to).

— The word can is used for statements of possibility and capability, whether material, physical, or

causal (can equals is able to).

1.4 Syntactic description

The main text uses the following conventions:

— Italicized font when a term is being defined

—

Constant-width font for examples, file names, and references to constants, especially 0, 1, x, and

z values

—

Boldface constant-width font for Verilog and SystemVerilog keywords, when referring to the

actual keyword

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IEEE

Std 1800-2005 IEEE STANDARD FOR S

YSTEMVERILOG:

The formal syntax of SystemVerilog is described using Backus-Naur Form (BNF). The following conven-

tions are used:

— Lowercase words, some containing embedded underscores, denote syntactic categories. For

example:

module_declaration

— Boldface-red characters denote reserved keywords, operators, and punctuation marks as a required

part of the syntax. For example:

module => ;

— A vertical bar ( | ) separates alternative items, unless it appears in boldface-red, in which case it

stands for itself. For example:

unary_operator ::=

+ | - | ! | ~ | & | ~& | | | ~| | ^ | ~^ | ^~

— Square brackets ([]) enclose optional items. For example:

input_declaration ::= input [ range ] list_of_variables ;

— Braces ( { } ) enclose a repeated item, unless it appears in boldface-red, in which case it stands for

itself. The item may appear zero or more times; the repetitions occur from left to right as with an

equivalent left-recursive rule. Thus, the following two rules are equivalent:

list_of_param_assignments ::= param_assignment { ,

param_assignment }

list_of_param_assignments ::=

param_assignment

| list_of_param_assignment , param_assignment

— If the name of any category starts with an italicized part, it is equivalent to the category name with-

out the italicized part. The italicized part is intended to convey some semantic information. For

example, “msb_index” and “lsb_index” are equivalent to “index.”

1.5 Use of color in this standard

This standard uses a minimal amount of color to enhance readability. The coloring is not essential and does

not affect the accuracy of this standard when viewed in pure black and white. The places where color is used

are the following:

— Cross references that are hyperlinked to other portions of this standard are shown in underlined-blue

text (hyperlinking works when this standard is viewed interactively as a PDF file).

— Syntactic keywords and tokens in the formal language definitions are shown in boldface-red text.

— Some figures use a minimal amount of color to enhance readability.

1.6 Contents of this standard

A synopsis of the clauses and annexes is presented as a quick reference. There are 31 clauses and 11

annexes. All clauses, as well as Annex A

through Annex I, are normative parts of this standard. Annex J and

Annex K

are included for informative purposes only.

Clause 1

describes the contents of this standard and the conventions used in this standard.

Clause 2

lists references to other standards that are required in order to implement this standard.

Clause 3

describes the lexical tokens used in SystemVerilog source text and their conventions. It describes

how to specify and interpret the lexical tokens.

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