Wideband Receiver for 5G,
Instrumentation, and ADEF
Brad Brannon, Steve Dorn, and Vandita Pai Raikar
Analog Devices, Inc.
Introduction
From the beginning, one of the biggest challenge to radio designers has
been the limitations of bandwidth. Early on, our radio forefathers thought
that frequencies above a few hundred kHz were of no value because of
detector limitations. Pioneers like Branly, Fessenden, Marconi, and many
others struggled with this, until Armstrong and Levy perfected heterodyn-
ing, opening higher frequencies of spectrum by downconverting to lower
frequencies that detectors could adequately process with technology of
the day. While higher frequencies were opened by the super-heterodyning
process, the bandwidth was still relatively limited.
Until recent years, processing more than a few 10s of MHz has been a
challenge and often limited to expensive solutions that often employed
massively paralleled radio technology. It has long been desirable to
simplify this and employ a method to simultaneously process as much
bandwidth as possible. This capability has slowly evolved over the last few
decades, as semiconductor processes and monolithic analog-to-digital
converter
(
ADC
)
architectures have matured. From modest beginnings in
the early ’90s until today, the direct RF sampling capability of ADCs has
increased from about 20 MHz of Nyquist bandwidth, to over 5 GHz with
products like the AD9213.
With the introduction of the AD9213 and the large instantaneous band-
width it supports, many new options are opened, not just for instrument-
grade receivers, but also for direct RF sampling radios, SIGINT, and radar.
Typical GSPS ADCs pose a unique challenge to overall performance,
because they are constructed from multiple ADCs cores that are run
in parallel to boost the net sample rate. Each of these converters must be
carefully timed and aligned and, even so, small errors between the con-
stituent converters generate numerous spectral artifacts.
1,2,3
Additionally,
ADCs must accurately track the analog input signals and carefully sample
and digitize them to prevent normal linear distortion. These two challenges,
interleaving and raw bandwidth, make design of wide bandwidth ADCs
very challenging where high fidelity is required, as in spectral applications
like advanced radio and instrumentation.
The AD9213 is up to the challenge because of the excellent linearity under
all signal conditions that is achieved by the implementation of on-chip
dithering and calibration, yielding both higher frequency operations and
performance. With a CW input at 4 GHz, the NSD is about –152 dBFS/Hz
and SFDR is typically better than 65 dBc, including second and third har-
monics. This enables true 5G instrument-grade receiver performance.
Figure 1. AD9213 12-bit, 10.25 GSPS RF ADC.
CLKVDD
(1.0 V)
CLK+
VCM
VIN–
VIN+
AVNN1
(–1.0 V)
AVDD2
(2.0 V)
AVDD1
(1.0 V)
DVDD
(1.0 V)
JVDD2
(2.0 V)
JVDD1
(1.0 V)
SERDOUT0±
SERDOUT15±
DGND
SYNCINB±
SYSREF±
Trigger
SVDD2
(2.0 V)
SERDOUT1±
…
AGND
CLK–
CLKGND
CLK
Synth
GPIO0, GPIO1,
GPIO3, GPIO4, GPIO5
SDIO SCLK
SPI Control
GPIO Assignment
Freq Hopping
Profile Select
Clock
Distribution
JESD204B
Subclass1
Control
JESD204B
Serializer
Tx Outputs
Signal
Monitor
Buffer
Digital
Gain Adj.
DDC+
Dec-by-N
AD9213
16
16
12
I/Q
CSB
ADC
Core
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TECHNICAL ARTICLE