降低同轴硅通孔诱导的禁止区域的创新方法

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"通过同轴硅通孔减少保持区的研究方法" 在微电子封装技术中，同轴硅通孔（Coaxial Through-Silicon-Via, TSV）被广泛用于三维集成电路，以实现高密度互连。然而，由于TSV产生的机械应力，会在周围区域产生所谓的“保持区”（Keep-Out-Zone, KOZ），这限制了芯片的有效利用空间。这篇研究论文，"An Effective Approach of Reducing the Keep-Out-Zone Induced by Coaxial Through-Silicon-Via"探讨了一种有效降低同轴TSV引起的保持区的新方法。作者Fengjuan Wang、Zhangming Zhu、Yintang Yang、Xiangkun Yin、Xiaoxian Liu和Ruixue Ding提出了一种名为同轴环形TSV（Coaxial-An annular TSV）的结构，它能够在不牺牲同轴TSV的电气性能的情况下，减少KOZ的影响。他们开发了一个适合分析由同轴和同轴环形TSV产生的热应力的模型，并通过有限元方法进行了验证。论文详细比较了同轴TSV和同轴环形TSV产生的保持区，揭示了环形结构如何有助于减小KOZ。此外，研究还考察了材料塑性、TSV材料、TSV尺寸以及同轴环形TSV内部金属镀层比例对保持区大小的影响。通过使用ANSYS'HFSS进行模拟，论文对比了不同TSV结构的电气特性，证明了同轴环形TSV的可行性。该研究不仅提供了一种优化TSV设计以减小KOZ的新策略，还对TSV制造工艺提出了建议，这对提高芯片集成度和系统性能具有重要意义。这一工作对于微电子工程领域的研究者和工程师来说，提供了重要的理论依据和技术参考，有助于推动3D集成电路的发展。

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2928 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 8, AUGUST 2014

An Effective Approach of Reducing the

Keep-Out-Zone Induced by Coaxial

Through-Silicon-Via

Fengjuan Wang, Zhangming Zhu, Member, IEEE, Yintang Yang, Xiangkun Yin, Xiaoxian Liu, and Ruixue Ding

Abstract—Keep-out-zone (KOZ) is a conservative way to pre-

vent any devices/cells from being impacted by the through-silicon-

via (TSV)-induced stress. In this paper, an effective approach

was proposed of reducing the KOZ induced by coaxial TSV, by

using the structure of coaxial-annular TSV, without decreasing

the electrical performance of coaxial TSV. The analytical model

was developed appropriate for the thermal stress induced by

both coaxial and coaxial-annular TSVs, and was veriﬁed by

the ﬁnite element method. The KOZs induced by coaxial and

coaxial-annular TSVs were compared in detail, and the effects

of Cu plasticity, TSV material, TSV size, and inner metal

plating ratio of coaxial-annular TSV were also studied. The

electrical characteristics of different TSVs were compared by

employing ANSYS’ HFSS, and a feasible fabrication process for

coaxial-annular TSV was suggested. It could be concluded that:

1) a 1.6-µ m (22.2%) drop of KOZ for coaxial-annular TSV could

be reached as compared with that of coaxial TSV; 2) coaxial-

annular TSV was proved to offer the same superior signal

integrity with coaxial TSV, improving S21 by about 93% at

5 GHz and 60% at 20 GHz compared with ordinary cylindrical

and annular TSVs; and 3) the coaxial-annular TSV is realizable.

Index Terms— 3-D, integration, keep-out-zone (KOZ), thermal

stress, through-silicon-via (TSV).

I. INTRODUCTION

ITH the continuous development of semiconductor

technology node, the conventional planar integrated

circuit (IC) scaling has reached limits that are difﬁcult to

surpass. The chip scaling and functionality increase result

in interconnect delay increase, limiting IC performance, and

increasing power consumption [1]. The 3-D integration has

emerged as an effective approach to enable smaller form

factor, higher performance, and lower power consumption

as opposed to conventional technologies [2], [3]. Through-

silicon-via (TSV) is the core technology that provides a verti-

cal interconnection with greatly reduced wire length among the

stacked dies [4]. However, due to the mismatch in coefﬁcient

Manuscript received January 6, 2014; accepted June 10, 2014. Date of

publication June 25, 2014; date of current version July 21, 2014. This

work was supported in part by the National Natural Science Foundation of

China under Grant 61322405, Grant 61204044, Grant 61376039, and Grant

61334003, in part by the National Key Basic Research Program of China

under Grant 2014CB33990, and in part by the Fundamental Research Funds

for the Central Universities under Grant K5051325005. The review of this

paper was arranged by Editor H. S. Momose.

The authors are with the School of Microelectronics, Xidian University,

Xi’an 710071, China (e-mail: zmyh@263.net).

Color versions of one or more of the ﬁgures in this paper are available

online at http://ieeexplore.ieee.org.

Digital Object Identiﬁer 10.1109/TED.2014.2330838

of thermal expansion (CTE) between TSV materials and

silicon, TSVs would induce mechanical stress in surrounding

silicon during the ﬁnal annealing and cooling step in the

manufacturing process ﬂow [5]–[10]. The stress can lead to an

emerging of keep-out-zone (KOZ) around TSV within which

no transistor is allowed to be placed, since the stresses are

very high and can adversely affect transistor performance and

reliability. Therefore, to quantify and minimize TSV-induced

KOZ is of signiﬁcant importance in the applications of TSVs

to 3-D ICs.

Ryu et al. [11] and Jiang et al. [12] quantiﬁed the

TSV-induced KOZ by analytical studies and ﬁnite element

method (FEM) simulations. References [13]–[15] investigated

the Cu TSV-induced KOZ through simulations and experi-

ments. Liao [16] reduced the TSV-induced KOZ (10×)by

the optimized novel trench structures near the TSV. Air-gap

structure was also used to achieve lower KOZ [17], [18]. The

TSV-induced stresses and KOZ for the dies in the packages

at the room temperature were calculated with FEM simula-

tion model. Shallow trench isolation (STI), which induces

compressive stress, can be used to absorb the TSV-induced

tensile stress, but TSV stress still has signiﬁcant impact on

device performance even after STI stress is considered [19].

What is more, [11]–[18] focuses on the ordinary cylindrical

TSV. There has been no literature on the minimization of

KOZ induced by coaxial TSV, which is well known for high

electrical performance [20]. In order to decrease the coaxial

TSV-induced KOZ, we propose an effective approach by

using the coaxial-annular TSV, which can provide predominant

thermo-mechanical performance, on the premise of offering

the same superior electrical transmission characterization as

coaxial TSV.

This paper is organized as follows. The thermo-mechanical

performances of coaxial and coaxial-annular TSVs are

compared in Section II. First, the analytical model of the

thermal stress induced by coaxial and coaxial-annular TSVs

is developed. Second, the analytical model is veriﬁed by

using FEM [21], and the stress distributions and KOZs are

compared induced by coaxial and coaxial-annular TSVs.

Third, the effects of Cu plasticity, TSV material, TSV size,

and inner metal plating ratio of coaxial-annular TSV are

studied in detail. In Section III, the electrical performances

of the different TSV structures are contrasted by employing

ANSYS’ HFSS [22], a 3-D full wave electromagnetic

simulator. The thin Ta layer, serving as diffusion barrier,

See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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