JESD204B TXRX数据手册：解扰、8/10B编码与CRC校验功能详解

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JESD204B TXRX 数据手册是一份由 Comcores 发布的用户手册，文档编号为 803-00003-01，修订版本为 6.19，发布日期为 2017 年 7 月 31日。这份手册主要关注 JESD204B 协议，这是一种在高性能数字信号处理系统中广泛使用的接口标准，特别适用于高速串行数据传输，包括解扰码、8/10B编码、时钟对齐、通道对齐以及CRC校验等关键技术。 1. 解扰码结构：JESD204B协议中包含解扰码功能，用于纠正或预防由于串行数据传输过程中可能发生的噪声干扰或比特错误。这通过一种算法来恢复原始数据的正确性，确保传输的可靠性。 2. 8/10B编码：这是一种编码方式，将8位数据转换成10位，增加了冗余位（如扰码），从而提高数据的抗噪声性能。8/10B编码有助于减少误码率，并在不牺牲数据速率的情况下提高信号质量。 3. 时钟对齐：JESD204B协议强调了时钟同步的重要性，确保发送和接收端的时钟信号保持同步，这对于保持数据流的稳定性和完整性至关重要。 4. 通道对齐：这意味着数据在多个并行通道上传输时，它们会按照特定的模式对齐，这有助于提高数据传输的效率和一致性，减少潜在的冲突和延迟。 5. CRC校验：循环冗余校验（CRC）是一种用于检测数据传输错误的校验技术。JESD204B中的CRC校验在数据接收端执行，如果发现错误，可以立即通知接收方，从而进行错误修正或者重新传输。 6. ADC采集数据：ADC（模拟到数字转换器）负责将模拟信号转换为数字信号，这些数字信号随后经过JESD204B协议的处理，包括编码、同步和校验，最终形成可被计算机或处理器理解的数字数据。 7. 文档修订历史：手册自2014年5月11日以来经历了多次修订，每次修订都针对不同的内容进行了更新，例如时钟特性、接口定义、新增功能（如PRBS和JTSPAT）、测试平台的改进，以及I2C定制接口的添加，反映了技术的不断发展和完善。 8. 接收部分的改进：在6.1版中，接收部分的解码器被更新，而在6.2版中，注册地址和参数列表进行了修正，进一步提高了数据接收的准确性。总结来说，JESD204B TXRX 数据手册详细介绍了如何利用这一接口标准实现高效的高速串行数据传输，以及如何通过关键功能如解扰码、编码和校验来确保数据的准确性和可靠性。同时，它还提供了关于如何配置和优化这个接口的深入指南，适合于从事高速数字信号处理系统的设计师和工程师参考。

JES204B IP Core – User Manual

Comcores ApS - Confidential 4

4. Receiver Module (Rx)

The function of the receiver module is to receive up to 24 lanes of high speed serialized data through the Serdes

interface and deliver it to the Custom Sample Interface, also known as Application Layer Interface, remapped

as a series of parallel samples.

Figure 3 – Receiver module's architecture

This is done by Rx modules as described above. The receiver is also responsible of emitting a Sync_b signal for

synchronization purposes.

The Receiver Module is separated in two main blocks according to the standard , Link Layer and Transport Layer.

The link layer is the main core whereas the transport layer can bu used to demap the samples received in the

link layer.

All the blocks of the receiver module are controlled by the registers shown in the upper part of the figure. Those,

interface with the CPU for control, configuration and monitoring purposes while the data stream goes directly

to the application. The communication with the registers is done entirely in the link layer.

4.1. Rx Generics

The generics are described in the Table 2 - Rx module generics.

Table 2 - Rx module generics

Signal name

Type

Range

Default

Description

Parameters Rx

JESD_MAST_INST

Boolean

0-1

Used in subclass2 mode to synchronize

local LMFC of multiple RX instances

JESD_DESKEW_BUF_ASIZE

Integer

3-8

Determines Depth of lane alignment buffer

per lane.

JESD_DESKEW_BUF_DSIZE

Integer

Data width of lane alignment buffer.

JESD_CSR_SELECT_MASK

Hex

000-FFF

000

Will be used to match slave_addr[31:24]

JES204B IP Core – User Manual

Comcores ApS - Confidential 5

Please note that most parameters have a heavy influence the size of the core. The user should take care not to

exceed the expected maximum values and while still maintaining flexibility.

In order to be able to limit the logic size when JESD_NO_SAMPLES is less than 8, a number of defines are set up

in the rx_transport/jesd_jesd204b_rx_transport_defines.v file. In this file, the user should comment out defines

for sample sizes not used.

4.2. Rx Top Level Interfaces

In this section, the top level interfaces port list is defined and a brief description of the functionality is also

included. This is intended as an overview of Rx’s top level interfaces. For an in-depth description, please refer

to section Functional Description where the detailed functionality is described. Ram interfaces are not included

in this section.

Table 3 – Rx top level port list

JESD_NO_LANES

Integer

1-24

Maximum number of enabled lanes per

device. Actual number of enabled lanes is

configurable through a register.

JESD_NO_SERDES_WORDS

Integer

1/2/4

User defined parameter to indicate serdes

data path width in terms of 10 bit symbols.

Valid values are 1,2,4

JESD_NO_FRAMES

Integer

1-256

Maximum number of bytes per frame (F).

The actual number is configurable through

JESD_NO_CONVERTERS

Integer

1-256

Maximum number of supported

converters (M). The actual number is

configurable through register access.

JESD_NO_CF

Integer

0-1

Maximum number of control words (CF)

per link. The actual number is configurable

through register access.

JESD_N_TOTAL

Integer

8-32

Maximum value of N’. The actual number

is configurable through register access.

Value increments in steps of 4.

JESD_N_MAX

Integer

8-32

Maximum value of sample width (N). The

actual number is configurable through

to JESD_N_TOTAL.

JESD_NO_SAMPLES

Integer

1-8

Maximum value of S (samples per

converter). The actual number is

configurable through register access.

JESD_SAMPLES_ON_IF

Integer

1-8

Number of samples per converter that will

be transmitted in parallel to/from the

custom sample interface. Valid values are

either 1 or JESD_NO_SAMPLES.

Signal name

Dir.

Width

Description

clk_character domain

clk_character

Device clock

sysref

System clock reference

Mapper interface (If only link layer is used see 6.6)

data_to_tl

32*JESD_NO_LANES

User data in form of JESD204B frames passed to

link layer. Bit[0] corresponds to the LSB of each

lane and bit [31] corresponds to the MSB of

each lane.

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