JESD204B应用指南:JESD204协议的介绍与应用建议

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JESD204B应用指南是一本提供实用JESD204技术信息、技巧和建议的指南，内容主要由全球数据转换器市场份额领导者Analog Devices提供。根据分析公司Databeans在2011年的数据转换器报告中指出，Analog Devices拥有48.5%的全球数据转换器市场份额，超过了其他八家竞争对手的总和。本指南的目的是帮助读者理解和掌握JESD204B标准，该标准是一种用于高速数据转换器与数字信号处理器之间高速数据传输的通信协议。该协议的广泛应用可以提高数据转换系统的性能和可靠性。首先，本指南介绍了什么是JESD204B以及为什么我们应该关注它。它解释了JESD204B的基本原理、工作方式和优势。通过深入了解JESD204B的特性和技术细节，读者可以更好地理解和应用该协议。接下来，本指南提供了从设计到调试的实用技巧和建议。它详细介绍了JESD204B的硬件要求、时钟管理、电路配置和信号完整性等方面的问题，并提供了解决这些问题的方法和策略。读者可以通过掌握这些技巧和建议，更好地设计和实施JESD204B应用，并解决可能遇到的问题和挑战。此外，本指南还包含了大量实际应用案例和典型问题的解决方案。通过这些案例和解决方案，读者可以了解JESD204B在不同领域和应用中的具体应用和效果。同时，读者还可以借鉴这些实例，根据自身需求和条件进行具体的应用和调整。最后，本指南还提供了JESD204B相关资源的链接和推荐。读者可以通过这些资源获取更多关于JESD204B的技术资料、文档和工具，进一步深入学习和应用该协议。总的来说，JESD204B应用指南是一本全面和实用的指南，为读者提供了深入理解和应用JESD204B的基础知识、技巧和建议。通过学习本指南，读者可以更好地应用JESD204B协议，提高数据转换系统的性能和可靠性，并解决可能遇到的问题和挑战。无论是初学者还是有经验的工程师，本指南都是一个宝贵的参考资料。

Technical Article MS-2442

Page 3 of 4

factor, which raises both design and manufacturing costs. In

some applications, the data converter interface becomes the

limiting factor in achieving the required system performance

in bandwidth hungry applications.

Figure 2. Ch

allenges in System Design and Interconnect Using Parallel

CMOS or LVDS

JESD204B OVERVIEW

The JESD204 data converter serial interface standard was

created by the JEDEC Solid State Technology Association

JC-16 Committee on Interface Technology with the goal of

providing a higher speed serial interface for data converters

to increase bandwidth and reduce the number of digital

inputs and outputs between high speed data converters and

other devices. The standard builds on 8b/10b encoding

technology developed by IBM that eliminates the need for a

frame clock and a data clock, enabling single line pair

communications at a much higher speed.

In 2006, JEDEC published the JESD204 specification for a

single 3.125 Gbps data lane. The JESD204 interface is self-

synchronous, so there is no need to calibrate the length of

the PCB wire traces to avoid clock skew. JESD204 leverages

the SerDes ports offered on many FPGAs to free up general-

purpose I/O.

JESD204A, published in 2008, adds support for multiple

time-aligned data lanes and lane synchronization. This

enhancement makes it possible to use higher bandwidth data

converters and multiple synchronized data converter channels

and is particularly important for wireless infrastructure

transceivers used in cellular base stations. JESD204A also

provides multidevice synchronization support which is

useful for devices, such as medical imaging systems, that

use large numbers of ADCs.

JESD204B, the third revision of the spec, increases the

maximum lane rate to 12.5 Gbps. JESD204B also adds

deterministic latency, which communicates synchronization

status between the receiver and transmitter. Harmonic clocking,

also introduced in JESD204B, makes it possible to derive a

high speed data converter clock from a lower speed input

clock with deterministic phasing.

SUMMARY

The JESD204B industry serial interface standard reduces the

number of digital inputs and outputs between high speed

data converters and FPGAs and other devices. Fewer

interconnects simplify layout and make it possible to achieve

a smaller form factor (see Figure 3). These advantages are

important for a wide range of high speed data converter

applications, such as wireless infrastructure transceivers,

software defined radios, medical imaging systems, and radar

and secure communications. Analog Devices, Inc., is an

original participating member of the JESD204 standards

committee and we have concurrently developed compliant data

converter technology and tools along with a comprehensive

product roadmap offering. By providing customers with

products that combine our cutting edge data converter

technology along with the JESD204A/JESD204B interface,

we expect to enable customers to solve their system design

problems, while taking advantage of this significant interfacing

breakthrough.

Figure 3. JESD204 with Its High Speed Serial I/O Capability Solves the System

PCB Complexity Challenge

ABOUT THE AUTHOR

George Diniz is a Product Line Manager in the High Speed

Digital-to-Analog Converters Group at Analog Devices

in Greensboro, NC. He leads a team responsible for the

development of JESD204B Rx and Tx interface cores, which

are integrated into high speed analog-to-digital and digital-

to-analog converter products. He has 25 years of experience

in the semiconductor industry and has held various roles in

design engineering and product line management. Before

joining ADI, George was a design engineer at IBM, where he

was engaged in mixed-signal design of custom SRAM macros,

PLL, and DLL functions for PowerPC processors. He has an

MSEE from North Carolina State University and a BEE from

Manhattan College. For recreation, George enjoys outdoor

activities, restoring automobiles, and running.

JESD204B Survival Guide

Technical Article

MS-2448

www.analog.

com

Grasp the Critical Issues for a

Functioning JESD204B

Interface

by Anthony Desimone, Applications Engineer, Analog

Devices, Inc., and Michael Giancioppo, Applications

Engineer, Analog Devices.

JESD204B is a recently approved JEDEC Standard for serial

data interfacing between converters and digital processing

devices. As a third-generation standard, it addresses some of

the limitations of the earlier versions. Among the benefits of

this interface are reductions in required board area for data

interface routing, reductions in setup and hold timing

requirements, and the enablement of smaller packages for

converter and logic devices. New analog/digital converters

from various vendors, such as the AD9250 from Analog

Devices, Inc., use this interface.

There is a trade-off to realizing the benefits of the JESD204B

interface, as it has complexities and subtleties which distinguish

it from existing interface formats and protocols. As with any

standard, it is clear that the interface must function seamlessly

to gain popularity and traction versus more common interfaces,

such as single data rate or double data rate CMOS or LVDS.

Although the JESD204B standard is documented by JEDEC,

some specific information about it is subject to interpretation

or may be spread over multiple references. It is also obvious

that it would be extremely helpful if there were a concise

guide that provided an overview of the standard, how it

works, and how to troubleshoot it if issues arise.

This article explains the interface from an ADC to FPGA for

JESD204B, how to identify when it’s working correctly, and,

perhaps more important, how to troubleshoot it if something

isn’t quite right. The troubleshooting techniques discussed

can use commonly available test and measurement equipment

including oscilloscopes and logic analyzers, along with software

tools such as the ChipScope from Xilinx® or SignalTap from

Altera®. Interface signaling is also explained to allow a single

approach or multiple approaches to visualize the signaling.

JESD204B OVERVIEW

The JESD204B standard provides a method to interface one

or multiple data converters to a digital-signal processing

device (typically, an ADC or DAC to an FPGA) over a higher

speed serial interface compared to the more typical parallel

data transfers. The interface, which runs at up to 12.5 Gbps/

lane, uses a framed serial data link with embedded clock and

alignment characters. The interface eases implementation of

the data interface of high speed converters by reducing the

number of traces between devices, thus reducing trace-

matching requirements, and removing setup- and hold-

timing constraint issues. Since a link needs to be established

prior to data transfer, there are new challenges and techniques

required to identify that the interface is working properly and, if

not, what to do.

Starting with a brief explanation of how the standard works,

the JESD204B interface uses three phases to establish the

synchronized link: code group synchronization (CGS), initial

lane synchronization (ILAS), and data transmission phase.

Required signals for the link are a shared reference clock

(device clock), at least one differential CML physical data

electrical connection (called a lane), and at least one other

synchronization signal (SYNC~ and possibly SYSREF). The

signals used depend upon the subclass:

• Subclass 0 uses device clock, lanes, and SYNC~

• Subclass 1 uses device clock, lanes, SYNC~, and

SYSREF

• Subclass 2 uses device clock, lanes, and SYNC~

Subclass 0 is adequate in many cases and will be the focus of

this article. Subclass 1 and Subclass 2 provide a method to

establish deterministic latency. This is important in application

when synchronizing multiple devices or system synchroniza-

tion or fixed latency is required (such as when a system needs a

known sampling edge for an event or an event must react to

an input signal within a specified time).

JESD204B Survival Guide

MS-2448 Technical Article

Page 2 of 7

Figure 1 shows a simplified JESD204B link from the Tx

device (ADC) to the Rx device (FPGA), with data from one

ADC going over one lane.

Although there are many variables within the JESD204B

specification, some have particular importance when

establishing a link. These key variables from the specification

are (note that these values are typically represented as “X − 1”):

• M: number of converters.

• L: number of physical lanes.

• F: number of octets per frame.

• K: number of frames per multiframe.

• N and N’: converter resolution and number of bits used

per sample (multiple of 4), respectively. N’ value is N

value, plus control and dummy bits.

SUBCLASS 0: SYNCHRONIZATION STEPS

As noted above, many applications can use the relatively

simpler Subclass 0 mode of operation. This is also the easiest

mode to establish and for which to verify a link. Subclass 0

uses three phases to establish and monitor synchronization:

CGS phase, ILAS phase, and data phase. The figures

associated with each phase present the data in different

formats, as they might be seen on an oscilloscope, logic

analyzer, or FPGA virtual I/O analyzer such as Xilinx

ChipScope or Altera SignalTap.

The Code Group Synchronization (CGS) Phase

The most significant parts of the CGS phase that can be

observed over the link are shown in Figure 2, along with a

description of the five highlighted points of the figure.

1. The Rx issues a synchronization request by driving the

SYNC~ pin low.

2. The Tx transmits /K28.5/ symbols (10 bits/symbol),

unscrambled beginning on the next symbol.

3. The Rx synchronizes when it receives at least four

consecutive /K28.5/ symbols without error and then the

Rx drives the SYNC~ pin high.

4. Rx must receive at least four 8B/10B characters without

error otherwise synchronization fails and the link stays

in CGS phase.

5. CGS Phase ends and ILAS phase begins.

The /K28.5/ character, also just known as /K/, within the

JESD204B standard can be exhibited as shown in Figure 3.

The standard requires a running neutral disparity. The

8B10B coding allows a balanced sequence that, on average,

contains an equal amount of 1’s and 0’s. Each 8B10B

character can have a positive (more 1’s) or negative (more

0’s) disparity, and the parity of the current character is

determined by the current sum of the previous characters

sent, and this is typically accomplished by alternately

transmitting a positive parity word, followed by a negative

parity word; the figure shows both polarities of the /K28.5/

symbol.

Figure 1. J

ESD204B Link Diagram for One ADC to an FPGA through One Lane

Figure 2. L

ogic Output of JESD204B Subclass 0 Link Signals During CGS Phase (Assumes Two Lanes, One Device with Two ADCs)

JESD204B Survival Guide

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