"TI CC1021产品手册：立即订购技术文档工具"

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DIO

LOCK

DCLK

RF_IN

LNA

FREQ

SYNTH

DIGITAL

DEMODULATOR

- Digital RSSI

- Gain Control

- Image Suppression

- Channel Filtering

- Demodulation

DIGITAL

MODULATOR

- Modulation

- Data shaping

- Power Control

BIAS

Power

Control

DIGITAL

INTERFACE

TO mC

CONTROL

LOGIC

ADC

RF_OUT

R_BIAS

XOSC_Q1 XOSC_Q2

PDO

XOSC

CHP_OUT

LNA 2

Multiplexer

PA_EN

LNA_EN

PCLK

PDI

PSEL

Not Recommended for New Designs NRND

CC1021

www.ti.com

SWRS045F –JANUARY 2006–REVISED NOVEMBER 2018

Submit Documentation Feedback

Product Folder Links: CC1021

5 Detailed Description

5.1 Overview

A simplified block diagram of the CC1021 device is shown in Figure 5-1. Only signal pins are shown.

The CC1021 device features a low-IF receiver. The received RF signal is amplified by the low-noise

amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF).

At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain

control, fine channel filtering, demodulation and bit synchronization is performed digitally. The CC1021

device outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the

DCLK pin. RSSI is available in digital format and can be read via the serial interface. The RSSI also

features a programmable carrier sense indicator.

In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output

is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian

filter can be used to obtain Gaussian FSK (GFSK).

The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for

generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO

operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and

VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal

is to be connected between XOSC_Q1 and XOSC_Q2. A lock signal is available from the PLL.

The 4-wire SPI serial interface is used for configuration.

5.2 Functional Block Diagram

Figure 5-1. CC1021 Device Simplified Block Diagram

Not Recommended for New Designs NRND

CC1021

www.ti.com

SWRS045F –JANUARY 2006–REVISED NOVEMBER 2018

Submit Documentation Feedback

Product Folder Links: CC1021

5.4 Microcontroller Interface

Used in a typical system, the CC1021 device will interface to a microcontroller. This microcontroller must

be able to:

• Program the CC1021 device into different modes via the 4-wire serial configuration interface (PDI,

PDO, PCLK and PSEL)

• Interface to the bi-directional synchronous data signal interface (DIO and DCLK)

• Optionally, the microcontroller can do data encoding / decoding

• Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status

or other status information.

• Optionally, the microcontroller can read back the digital RSSI value and other status information via the

4-wire serial interface.

5.4.1 Configuration Interface

The microcontroller interface is shown in Figure 5-3. The microcontroller uses 3 or 4 I/O pins for the

configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input.

PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are

connected together and a bi-directional pin is used at the microcontroller.

The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the

configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is

not activated (active low).

PSEL has an internal pullup resistor and should be left open (tri-stated by the microcontroller) or set to a

high level during power down mode in order to prevent a trickle current flowing in the pullup.

Figure 5-3. Microcontroller Interface

5.4.2 Signal Interface

A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the

data timing should be connected to a microcontroller input.

As an option, the data output in receive mode can be made available on a separate pin. See Section 5.6

further details.

5.4.3 PLL Lock Signal

Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic

level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test

signals.

PCLK

PDI

PSEL

Address Write mode

6 5 4 3 2 1 0

5 4

2 1

Data byte

CL,min

CH,min

PDO

Not Recommended for New Designs NRND

CC1021

SWRS045F –JANUARY 2006–REVISED NOVEMBER 2018

www.ti.com

Submit Documentation Feedback

Product Folder Links: CC1021

5.5 4-wire Serial Configuration Interface

The CC1021 device is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and

PSEL) where the CC1021 device is the slave. There are 8-bit configuration registers, each addressed by a

7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of the CC1021

device requires sending 33 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time

needed for a full configuration depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full

configuration is done in less than 53 ms. Setting the device in power down mode requires sending one

frame only and will in this case take less than 2 ms. All registers are also readable.

During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data

frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the

first bit. The next bit is the R/W bit (high for write, low for read). The 8 data-bits are then transferred

(D7:0). During address and data transfer the PSEL (Program SELect) must be kept low. See Figure 5-4.

The timing for the programming is also shown in Figure 5-4 with reference to Table 5-1. The clocking of

the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of

PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is

loaded into the internal configuration register.

The configuration data will be retained during a programmed power down mode, but not when the power

supply is turned off. The registers can be programmed in any order.

The configuration registers can also be read by the microcontroller via the same configuration interface.

The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. The CC1021

device then returns the data from the addressed register. PDO is used as the data output and must be

configured as an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be

sampled at the positive edge. The read operation is illustrated in Figure 5-5.

PSEL must be set high between each read/write operation.

Figure 5-4. Configuration Registers Write Operation

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