DDR2数据手册：时序分析与IP设置指南

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DDR2 (Double Data Rate Two) SDRAM（同步动态随机存取内存）是一种高速内存技术，广泛应用于计算机系统中，特别是对于需要高性能数据传输的应用。本数据手册由Altera公司发布，提供了详细的控制器用户指南，适用于软件版本9.0，发布日期为2009年3月。它涵盖了DDR2时序分析、功能描述以及IP（知识产权）参数设置等关键知识点。 1. **DDR2时序分析**： DDR2时序参数对于确保内存系统的稳定性和性能至关重要。这些参数包括但不限于CK（时钟周期）、TCDQ（典型数据延迟）、tRCD（列预充电时间）、tRP（行预充电时间）等。理解并优化这些时序有助于避免信号抖动、提高数据吞吐量和降低功耗。时序分析通常涉及确定并满足内存规范中规定的最小和最大延迟要求，以确保系统能正常运行。 2. **功能描述**： DDR2 SDRAM控制器的主要功能包括数据读写操作、地址解码、时钟管理、命令处理和错误检测/纠正。它能够支持多种模式，如单通道、双通道甚至四通道，以实现更高的带宽。控制器还负责控制信号的时钟相位调整，确保正确的数据通信。此外，它还支持不同频率和容量的内存模块，具有灵活的配置选项。 3. **IP参数设置**：在使用DDR2 SDRAM控制器时，用户需要设置一系列参数，如工作频率、内存类型（如DDR2-667、DDR2-800等）、内存宽度、CAS latency（列地址延迟）等。这需要对硬件和软件接口有深入理解，以确保正确配置，避免潜在的兼容性问题。参数设置可能涉及到硬件寄存器编程或通过高级设计工具进行，以匹配具体应用的需求。 4. **版权和责任声明**： Altra Corporation保留所有权利，并指出其商标和服务标记的使用情况。他们提供标准保修，但保留在任何时候对产品和服务进行更新的权利，而不必提前通知用户。此外，用户在使用手册中的信息、产品或服务时，必须遵循Altera的书面协议，否则将不承担任何责任或义务。此DDR2数据手册为设计者和工程师提供了宝贵的参考资料，帮助他们掌握DDR2内存技术的使用，优化系统性能，并确保合规性。理解和正确配置这些参数是构建高效、稳定的系统的关键。

Chapter 2: Getting Started 2–3

SOPC Builder Flow

f For detailed explanation of the parameters, refer to the “Parameter

Settings” on page 3–1.

6. Click Finish to complete the DDR and DDR2 SDRAM High-Performance

Controller MegaCore function and add it to the system.

Complete the SOPC Builder System

To complete the SOPC Builder system, follow these steps:

1. In the System Contents tab, select Nios II Processor and click Add.

2. On the Nios II Processor page, in the Core Nios II tab, select altmemddr for Reset

Vector and Exception Vector.

3. Change the Reset Vector Offset and the Exception Vector Offset to an Avalon

address that is not written to by the ALTMEMPHY megafunction during its

calibration process.

c The ALTMEMPHY megafunction performs memory interface calibration

every time it is reset, and in doing so, writes to a range of addresses. If you

want your memory contents to remain intact through a system reset, you

should avoid using these memory addresses. This step is not necessary, if

you reload your SDRAM memory contents from flash every time you reset.

To calculate the Avalon-MM address equivalent of the memory address range 0×0

to 0×1f, multiply the memory address by the width of the memory interface data

bus in bytes. For example, if your external memory data width is 8 bits in non-AFI

mode, then the Reset Vector Offset should be 0×20 and the Exception Vector

Offset should be 0x40. Refer to Table 2–2 for more Avalon-MM addresses for AFI

and non-AFI modes.

4. Click Finish.

5. On the System Contents tab, expand Interface Protocols and expand Serial.

6. Select JTAG UART and click Add.

7. Click Finish.

1 If there are warnings about overlapping addresses, on the System menu,

click Auto Assign Base Addresses.

If you enable ECC and there are warnings about overlapping IRQs, on the

System menu click Auto Assign IRQs.

Table 2–2. Avalon-MM Addresses for AFI and Non-AFI mode

External Memory

Interface Width

Reset Vector Offset Exception Vector Offset

AFI Non-AFI AFI Non-AFI

8 0×40 0×20 0×60 0×40

16 0×80 0×40 0×A0 0×60

32 0×100 0×80 0×120 0×A0

64 0×200 0×100 0×220 0×120

2–4 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

DDR and DDR2 SDRAM High-Performance Controller User Guide © March 2009 Altera Corporation

8. For this example system, ensure all the other modules are clocked on the

altmemddr_sysclk, to avoid any unnecessary clock-domain crossing logic.

9. Click Generate.

1 Among the files generated by SOPC Builder is the Quartus II IP File (.qip).

This file contains information about a generated IP core or system. In most

cases, the .qip file contains all of the necessary assignments and

information required to process the MegaCore function or system in the

Quartus II compiler. Generally, a single .qip file is generated for each SOPC

Builder system. However, some more complex SOPC Builder components

generate a separate .qip file. In that case, the system .qip file references the

component .qip file.

10. Compile your design, refer to “Compile the Design” on page 2–13.

c If you are upgrading your Nios system design from version 8.1 or previous ,

ensure that you change the Reset Vector Offset and the Exception Vector

Offset to AFI mode.

Simulate the System

During system generation, SOPC Builder optionally generates a simulation model

and testbench for the entire system, which you can use to easily simulate your system

in any of Altera's supported simulation tools. SOPC Builder also generates a set of

ModelSim

Tcl scripts and macros that you can use to compile the testbench, IP

functional simulation models, and plain-text RTL design files that describe your

system in the ModelSim simulation software.

f For more information about simulating SOPC Builder systems, refer to volume 4 of

the Quartus II Handbook and AN 351: Simulating Nios II Systems.

MegaWizard Plug-In Manager Flow

The MegaWizard Plug-In Manager flow allows you to customize the DDR and DDR2

SDRAM High-Performance Controller MegaCore function, and manually integrate

the function into your design.

1 You can alternatively use the IP Advisor to help you start your DDR and DDR2

SDRAM High-Performance Controller MegaCore design. On the Quartus II Tools

menu, point to Advisors, and then click IP Advisor. The IP Advisor guides you

through a series of recommendations for selecting, parameterizing, evaluating, and

instantiating a DDR and DDR2 SDRAM High-Performance Controller MegaCore

function into your design. It then guides you through a complete Quartus II

compilation of your project.

f For more information about the MegaWizard Plug-In Manager and the IP Advisor,

refer to the Quartus II Help.

Chapter 2: Getting Started 2–5

MegaWizard Plug-In Manager Flow

Specify Parameters

To specify DDR or DDR2 SDRAM High-Performance Controller parameters using the

MegaWizard Plug-In Manager flow, follow these steps:

1. In the Quartus II software, create a new Quartus II project with the New Project

Wizard.

2. On the Tools menu, click MegaWizard Plug-In Manager and follow the steps to

start the MegaWizard Plug-In Manager.

1 The DDR or DDR2 SDRAM High-Performance Controller MegaCore

function is in the Interfaces folder under the Memory Controllers folder.

3. Specify the parameters on all pages in the Parameter Settings tab.

f For detailed explanation of the parameters, refer to the “Parameter

Settings” on page 3–1.

4. On the EDA tab, turn on Generate simulation model to generate an IP functional

simulation model for the MegaCore function in the selected language.

An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL

model produced by the Quartus II software.

c Use the simulation models only for simulation and not for synthesis or any

other purposes. Using these models for synthesis creates a nonfunctional

design.

1 Some third-party synthesis tools can use a netlist that contains only the

structure of the MegaCore function, but not detailed logic, to optimize

performance of the design that contains the MegaCore function. If your

synthesis tool supports this feature, turn on Generate netlist.

5. On the Summary tab, select the files you want to generate. A gray checkmark

indicates a file that is automatically generated. All other files are optional.

f For more information about the files generated in your project directory,

refer to Table 2–3.

6. Click Finish to generate the MegaCore function and supporting files.

7. If you generate the MegaCore function instance in a Quartus II project, you are

prompted to add the .qip files to the current Quartus II project. When prompted to

add the .qip files to your project, click Yes. The addition of the .qip files enables

their visibility to Nativelink. Nativelink requires the .qip files to include libraries

for simulation.

1 The .qip file is generated by the MegaWizard interface, and contains

information about the generated IP core. In most cases, the .qip file contains

all of the necessary assignments and information required to process the

MegaCore function or system in the Quartus II compiler. The MegaWizard

interface generates a single .qip file for each MegaCore function.

2–6 Chapter 2: Getting Started

MegaWizard Plug-In Manager Flow

8. After you review the generation report, click Exit to close the MegaWizard Plug-In

Manager.

Table 2–3 describes the generated files and other files (AFI mode) that may be in

your project directory. The names and types of files specified in the MegaWizard

Plug-In Manager report vary based on whether you created your design with

VHDL or Verilog HDL.

Table 2–3. Generated Files (Part 1 of 2)

Filename Description

<variation name>.bsf Quartus II symbol file for the MegaCore function

variation. You can use this file in the Quartus II block

diagram editor.

<variation name>.html MegaCore function report file.

<variation name>.v or .vhd A MegaCore function variation file, which defines a

VHDL or Verilog HDL top-level description of the

custom MegaCore function. Instantiate the entity

defined by this file inside of your design. Include this

file when compiling your design in the Quartus II

software.

<variation name>.qip Contains Quartus II project information for your

MegaCore function variations.

<variation name>.ppf This XML file describes the MegaCore pin attributes to

the Quartus II Pin Planner. MegaCore pin attributes

include pin direction, location, I/O standard

assignments, and drive strength. If you launch IP

Toolbench outside of the Pin Planner application, you

must explicitly load this file to use Pin Planner.

<variation name>_auk_ddr_hp_controller_wrapper.vo or .vho VHDL or Verilog HDL IP functional simulation model.

<variation name>_example_driver.v or .vhd Example self-checking test generator that matches

your variation.

<variation name>_example_top.v or .vhd Example top-level design file that you should set as

your Quartus II project top level. Instantiates the

example driver and the controller.

alt_mem_phy_defines.v Contains constants used in the interface. This file is

always in Verilog HDL regardless of the language you

chose in the MegaWizard Plug-In Manager.

<variation_name>_phy.html Lists the top-level files created and ports used in the

megafunction.

<variation_name>_phy.v/.vhd Top-level file of your ALTMEMPHY variation, generated

based on the language you chose in the MegaWizard

Plug-In Manager.

<variation_name>_phy.vho Contains functional simulation model for VHDL only.

<variation_name>_phy_alt_mem_phy_delay.vhd Includes a delay module for simulation. This file is only

generated if you choose VHDL as the language of your

MegaWizard Plug-In Manager output files.

<variation_name>_phy_alt_mem_phy_dq_dqs.vhd or .v Generated file that contains DQ/DQS I/O atoms

interconnects and instance. Arria II GX devices only.

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