数字逻辑设计基础与Verilog实现(第2版)

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"McGraw Hill 的《Fundamentals of Digital Logic with Verilog Design(2nd Edition)》是一本针对电气与计算机工程初学者的数字逻辑设计教材。本书旨在平衡基本概念的教学和实践应用，通过包含的CAD软件来促进学习过程。作者意在避免传统教材中涵盖过多材料导致的问题，而是深入浅出地教授数字逻辑的基础概念，并使用CAD工具展示现代数字电路设计方法。书中通过简单电路设计实例引入基本概念，先使用手动技术，再结合现代CAD工具进行更复杂的示例分析，强调现代设计方法的实际应用。" 该书的主要目标有两个：一是教育学生掌握经典的、手动的数字逻辑设计基础概念；二是清晰地展示当今使用CAD工具进行数字电路设计的过程。尽管现代设计师很少使用手动技术，但这些技术能帮助学生直观理解数字电路的工作原理，并理解CAD工具如何简化设计过程。《数字逻辑与Verilog设计基础》由Stephen Brown和Zvonko Vranesic撰写，他们来自多伦多大学电气与计算机工程系。这本书由McGraw-Hill Higher Education出版，是该公司的高等教育分部之一，反映了出版社对教育领域的持续贡献。书中内容覆盖了Verilog编程语言在数字逻辑设计中的应用，以及如何利用这种硬件描述语言进行数字系统的设计和验证。读者将学习如何使用Verilog进行逻辑门级建模、组合逻辑和时序逻辑的设计，以及如何构建更复杂的数字系统，如触发器、计数器和存储器。此外，书中还可能涵盖了以下知识点： 1. 数字逻辑基础：二进制数系统、布尔代数、逻辑门（AND, OR, NOT, XOR等）。 2. 组合逻辑电路：半加器、全加器、编码器、解码器、多路复用器等。 3. 时序逻辑：触发器（D, JK, T, RS等）、计数器（模N计数器、同步计数器、异步计数器等）、移位寄存器。 4. 数字系统设计：数据路径、控制逻辑、微程序控制、硬连线控制。 5. Verilog语法和结构：模块定义、连续赋值、结构体、操作符、进程（always块）。 6. 数字系统验证：仿真、综合、功能验证、时序验证。 7. 实验和项目：学生将有机会通过实际操作加深对理论知识的理解。通过这本教材，学生不仅能掌握数字逻辑设计的基本理论，还能获得实际使用CAD工具进行设计和验证的实践经验，从而更好地适应现代电子工程领域的需求。

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xviii Contents

Problems 434

References 442

Chapter 8

Synchronous Sequential

Circuits 445

8.1 Basic Design Steps 447

8.1.1 State Diagram 447

8.1.2 State Table 449

8.1.3 State Assignment 449

8.1.4 Choice of Flip-Flops and Derivation

of Next-State and Output

Expressions 451

8.1.5 Timing Diagram 453

8.1.6 Summary of Design Steps 454

8.2 State-Assignment Problem 458

8.2.1 One-Hot Encoding 460

8.3 Mealy State Model 462

8.4 Design of Finite State Machines Using CAD

Tools 467

8.4.1 Verilog Code for Moore-Type

FSMs 467

8.4.2 Synthesis of Verilog Code 468

8.4.3 Simulating and Testing the Circuit 470

8.4.4 Alternative Styles of Verilog Code 471

8.4.5 Summary of Design Steps When Using

CAD Tools 473

8.4.6 Specifying the State Assignment in

Verilog Code 474

8.4.7 Speciﬁcation of Mealy FSMs Using

Verilog 475

8.5 Serial Adder Example 477

8.5.1 Mealy-Type FSM for Serial Adder 477

8.5.2 Moore-Type FSM for Serial Adder 479

8.5.3 Verilog Code for the Serial Adder 480

8.6 State Minimization 486

8.6.1 Partitioning Minimization

Procedure 486

8.6.2 Incompletely Speciﬁed FSMs 493

8.7 Design of a Counter Using the Sequential

Circuit Approach 495

8.7.1 State Diagram and State Table

for a Modulo-8 Counter 495

8.7.2 State Assignment 496

8.7.3 Implementation Using D-Type

Flip-Flops 497

8.7.4 Implementation Using JK-Type

Flip-Flops 498

8.7.5 Example—A Different Counter 502

8.8 FSM as an Arbiter Circuit 505

8.8.1 Implementation of the Arbiter

Circuit 508

8.8.2 Minimizing the Output Delays

for an FSM 511

8.8.3 Summary 511

8.9 Analysis of Synchronous Sequential

Circuits 512

8.10 Algorithmic State Machine (ASM)

Charts 516

8.11 Formal Model for Sequential Circuits 519

8.12 Concluding Remarks 521

Problems 521

References 525

Chapter 9

Asynchronous Sequential

Circuits 527

9.1 Asynchronous Behavior 528

9.2 Analysis of Asynchronous Circuits 531

9.3 Synthesis of Asynchronous Circuits 540

9.4 State Reduction 553

9.5 State Assignment 568

9.5.1 Transition Diagram 571

9.5.2 Exploiting Unspeciﬁed Next-State

Entries 574

9.5.3 State Assignment Using Additional

State Variables 578

9.5.4 One-Hot State Assignment 582

9.6 Hazards 584

9.6.1 Static Hazards 585

9.6.2 Dynamic Hazards 590

9.6.3 Signiﬁcance of Hazards 592

9.7 A Complete Design Example 592

9.7.1 The Vending-Machine Controller 592

9.8 Concluding Remarks 599

Problems 599

References 604

Chapter 10

Digital System Design 605

10.1 Building Block Circuits 606

10.1.1 Flip-Flops and Registers with Enable

Inputs 606

10.1.2 Shift Registers with Enable

Inputs 607

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Contents xix

10.1.3 Static Random Access Memory

(SRAM) 609

10.1.4 SRAM Blocks in PLDs 611

10.2 Design Examples 612

10.2.1 A Bit-Counting Circuit 612

10.2.2 ASM-Chart-Implied Timing

Information 613

10.2.3 Shift-and-Add Multiplier 618

10.2.4 Divider 623

10.2.5 Arithmetic Mean 631

10.2.6 Sort Operation 641

10.3 Clock Synchronization 653

10.3.1 Clock Skew 653

10.3.2 Flip-Flop Timing Parameters 655

10.3.3 Asynchronous Inputs to Flip-Flops 656

10.3.4 Switch Debouncing 657

10.4 Concluding Remarks 659

Problems 659

References 663

Chapter 11

Testing of Logic Circuits 665

11.1 Fault Model 666

11.1.1 Stuck-at Model 666

11.1.2 Single and Multiple Faults 667

11.1.3 CMOS Circuits 667

11.2 Complexity of a Test Set 667

11.3 Path Sensitizing 669

11.3.1 Detection of a Speciﬁc Fault 671

11.4 Circuits with Tree Structure 673

11.5 Random Tests 674

11.6 Testing of Sequential Circuits 677

11.6.1 Design for Testability 677

11.7 Built-in Self-Test 681

11.7.1 Built-in Logic Block Observer 685

11.7.2 Signature Analysis 687

11.7.3 Boundary Scan 688

11.8 Printed Circuit Boards 688

11.8.1 Testing of PCBs 690

11.8.2 Instrumentation 691

11.9 Concluding Remarks 692

Problems 692

References 695

Appendix A

Verilog Reference 697

A.1 Documentation in Verilog Code 699

A.2 White Space 699

A.3 Signals in Verilog Code 699

A.4 Identiﬁer Names 699

A.5 Signal Values, Numbers, and Parameters 700

A.6 Net and Variable Types 701

A.6.1 Nets 701

A.6.2 Variables 702

A.6.3 Memories 703

A.7 Operators 703

A.8 Verilog Module 705

A.9 Gate Instantiations 706

A.10 Concurrent Statements 708

A.10.1 Continuous Assignments 709

A.10.2 Using Parameters 710

A.11 Procedural Statements 711

A.11.1 Always and Initial Blocks 711

A.11.2 The If-Else Statement 713

A.11.3 Statement Ordering 714

A.11.4 The Case Statement 715

A.11.5 Casex and Casez Statements 717

A.11.6 Loop Statements 717

A.11.7 Blocking versus Non-blocking

Assignments for Combinational

Circuits 721

A.12 Using Subcircuits 721

A.12.1 Subcircuit Parameters 723

A.12.2 Verilog 2001 Generate Capability 725

A.13 Functions and Tasks 726

A.14 Sequential Circuits 730

A.14.1 A Gated D Latch 730

A.14.2 D Flip-Flop 730

A.14.3 Flip-Flops with Reset 731

A.14.4 Instantiating a Flip-Flop from a

Library 732

A.14.5 Registers 733

A.14.6 Shift Registers 734

A.14.7 Counters 735

A.14.8 An Example of a Sequential

Circuit 736

A.14.9 Moore-Type Finite State

Machines 737

A.14.10 Mealy-Type Finite State

Machines 739

A.15 Guidelines for Writing Verilog Code 742

A.16 MAX+PlusII Verilog Support 745

A.16.1 Limitations in MAX+PlusII 745

A.17 Concluding Remarks 746

References 746

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xx Contents

Appendix B

Tutorial 1 747

B.1 Introduction 748

B.1.1 Getting Started 748

B.2 Design Entry Using Schematic

Capture 751

B.2.1 Specifying the Project Name 752

B.2.2 Using the Graphic Editor 752

B.2.3 Synthesizing a Circuit from the

Schematic 758

B.2.4 Performing Functional Simulation 759

B.2.5 Using the Message Processor to Locate

and Fix Errors 763

B.3 Design Entry Using Verilog 765

B.3.1 Specifying the Project Name 765

B.3.2 Using the Text Editor 765

B.3.3 Synthesizing a Circuit from the Verilog

Code 767

B.3.4 Performing Functional Simulation 767

B.3.5 Using the Message Processor to Debug

Verilog Code 768

B.4 Design Entry Using Truth Tables 768

B.4.1 Using the Waveform Editor 769

B.4.2 Create the Timing Diagram 769

B.4.3 Synthesizing a Circuit from the

Waveforms 770

B.5 Mixing Design-Entry Methods 772

B.5.1 Creating a Schematic that Includes a

Truth Table 772

B.5.2 Synthesizing and Simulating a Circuit

from the Schematic 774

B.5.3 Using the Hierarchy Display 775

B.5.4 Concluding Remarks 775

Appendix C

Tutorial 2 777

C.1 Implementing a Circuit

in a MAX 7000 CPLD 778

C.1.1 Using the Compiler 779

C.1.2 Selecting a Chip 780

C.1.3 Viewing the Logic Synthesis

Options 781

C.1.4 Examining the Implemented

Circuit 782

C.1.5 Running the Timing Simulator 783

C.1.6 Using the Floorplan Editor 784

C.2 Implementing a Circuit in a FLEX 10K

FPGA 787

C.3 Downloading a Circuit into a Device 789

C.4 Making Pin Assignments 790

C.4.1 Assigning Signals to Pins in the

Floorplan Editor 792

C.4.2 Making Pin Assignments

Permanent 794

C.5 Concluding Remarks 795

Appendix D

Tutorial 3 797

D.1 Design Using Verilog Code 798

D.1.1 The Ripple-Carry Adder Code 798

D.1.2 Using the Timing Analyzer

Module 801

D.2 Using an LPM Module 802

D.3 Design of a Sequential Circuit 806

D.3.1 Using the Graphic Editor 806

D.3.2 Synthesizing a Circuit and Using the

Timing Simulator 812

D.3.3 Using the Timing Analyzer 813

D.3.4 Using Verilog Code 814

D.4 Design of a Finite State Machine 815

D.4.1 Implementation in a CPLD 815

D.4.2 Implementation in an FPGA 816

D.5 Concluding Remarks 819

Appendix E

Commercial Devices 821

E.1 Simple PLDs 822

E.1.1 The 22V10 PAL Device 822

E.2 Complex PLDs 824

E.2.1 Altera MAX 7000 825

E.3 Field-Programmable Gate Arrays 826

E.3.1 Altera FLEX 10K 827

E.3.2 Xilinx XC4000 830

E.3.3 Altera APEX 20K 831

E.3.4 Altera Stratix 832

E.3.5 Xilix Virtex 834

E.4 Transistor-Transistor Logic 835

E.4.1 TTL Circuit Families 836

References 837

Index 838

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2 CHAPTER 1

•

Design Concepts

This book is about logic circuits—the circuits from which computers are built. Proper understanding of

logic circuits is vital for today’s electrical and computer engineers. These circuits are the key ingredient of

computers and are also used in many other applications. They are found in commonly used products, such as

digital watches, various household appliances, CD players, and electronic games, as well as in large systems,

such as the equipment for telephone and television networks.

The material in this book will introduce the reader to the many issues involved in the design of logic

circuits. It explains the key ideas with simple examples and shows how complex circuits can be derived from

elementary ones. We cover the classical theory used in the design of logic circuits in great depth because it

provides the reader with an intuitive understanding of the nature of such circuits. But throughout the book we

also illustrate the modern way of designing logic circuits, using sophisticated computer aided design (CAD)

software tools. The CAD methodology adopted in the book is based on the industry-standard design language

called Verilog. Design with Verilog is ﬁrst introduced in Chapter 2, and usage of Verilog and CAD tools is

an integral part of each chapter in the book.

Logic circuits are implemented electronically, using transistors on an integrated circuit chip. With modern

technology it is possible to fabricate chips that contain tens of millions of transistors, as in the case of computer

processors. The basic building blocks for such circuits are easy to understand, but there is nothing simple

about a circuit that contains tens of millions of transistors. The complexity that comes with the large size of

logic circuits can be handled successfully only by using highly organized design techniques. We introduce

these techniques in this chapter, but ﬁrst we brieﬂy describe the hardware technology used to build logic

circuits.

1.1 Digital Hardware

Logic circuits are used to build computer hardware, as well as many other types of products.

All such products are broadly classiﬁedas digital hardware. The reasonthat the name digital

is used will become clear later in the book—it derives from the way in which information

is represented in computers, as electronic signals that correspond to digits of information.

The technology used to build digital hardware has evolved dramatically over the past

four decades. Until the 1960s logic circuits were constructed with bulky components, such

as transistors and resistors that came as individual parts. The advent of integrated circuits

made it possible to place a number of transistors, and thus an entire circuit, on a single

chip. In the beginning these circuits had only a few transistors, but as the technology

improved they became larger. Integrated circuit chips are manufactured on a silicon wafer,

such as the one shown in Figure 1.1. The wafer is cut to produce the individual chips,

which are then placed inside a special type of chip package. By 1970 it was possible to

implement all circuitry needed to realize a microprocessor on a single chip. Although early

microprocessors had modest computing capability by today’s standards, they opened the

door for the information processing revolution by providing the means for implementation

of affordable personal computers. About 30 years ago Gordon Moore, chairman of Intel

Corporation, observed that integrated circuit technology was progressing at an astounding

rate, doubling the number of transistors that could be placed on a chip every 1.5 to 2 years.

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