MPC5643L：高性能双核处理器，具备ECC内存和安全特性

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MPC5643L是一款由Freescale Semiconductor公司生产的高性能e200z4双核微处理器，采用32位Power Architecture®技术。这款芯片的主要特性包括： 1. **核心架构**: - 高性能：双核设计，每个核心频率可高达120MHz，支持五级流水线处理，实现高效率计算。 - **指令集**: 提供变量长度编码（VLE），有利于优化代码执行效率。 2. **内存管理与缓存**: - 内存管理单元（MMU）：增强了内存访问控制和虚拟内存支持。 - 4KB带错误检测代码的指令缓存：提高了程序执行速度并提供错误检查功能。 3. **信号处理能力**: - 包含信号处理引擎（SPE），这是一类专用硬件加速器，用于高效处理特定类型的计算任务。 4. **存储选项**: - 1MB闪存内存，具有错误校验码（ECC），确保数据的可靠性。 - 128KB片上静态随机访问存储器（SRAM），同样带有ECC保护。 - 内置读写一次（RWW）功能，可以模拟只读存储器（EEPROM），方便数据持久化。 5. **安全特性**: - 实现了先进的安全概念，如锁步模式和故障安全保护，提高系统稳定性。 - **Sphere of Replication (SoR)**：对关键组件如CPU核心、EDMA（外设直接内存访问）控制器和交叉bar交换机等进行冗余复制，增强系统的容错性。 - **Fault Collection and Control Unit (FCCU)**：用于故障检测和处理，确保在异常情况下能快速恢复。 6. **封装形式**: - 多种封装类型可供选择，如TBD封装（可能指未定义或待定）、MAPBGA-225（15mmx15mm）、QFN12封装（尺寸待定）、SOT-343R（尺寸待定）以及144LQFP封装（14x14mmx0.8mm）和257MAPBGA（尺寸待定，但提及深度为14x14x0.8mm）。值得注意的是，该芯片处于开发阶段，Freescale半导体保留随时更改产品或停止供应的权利。提供的文档（MPC5643L Rev.9, 6/2013）是先进信息文档，包含了关于该产品的详细规格和技术细节，但用户在购买和应用时应考虑其最终产品状态和官方发布的产品手册。

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor16

— Individual programmable filters for each mailbox

— 8 mailboxes configurable as a 6-entry receive FIFO

— 8 programmable acceptance filters for receive FIFO

• Programmable clock source

— System clock

— Direct oscillator clock to avoid FMPLL jitter

1.5.27 FlexRay

The FlexRay module provides the following features:

• Full implementation of FlexRay Protocol Specification 2.1 Rev. A

• 64 configurable message buffers can be handled

• Dual channel or single channel mode of operation, each as fast as 10 Mbit/s data rate

• Message buffers configurable as transmit or receive

• Message buffer size configurable

• Message filtering for all message buffers based on Frame ID, cycle count, and message ID

• Programmable acceptance filters for receive FIFO

• Message buffer header, status, and payload data stored in system memory (SRAM)

• Internal FlexRay memories have error detection and correction

1.5.28 Serial communication interface module (LINFlexD)

The LINFlexD module (LINFlex with DMA support) on this device features the following:

• Supports LIN Master mode, LIN Slave mode and UART mode

• LIN state machine compliant to LIN1.3, 2.0, and 2.1 specifications

• Manages LIN frame transmission and reception without CPU intervention

• LIN features

— Autonomous LIN frame handling

— Message buffer to store as many as 8 data bytes

— Supports messages as long as 64 bytes

— Detection and flagging of LIN errors (Sync field, delimiter, ID parity, bit framing, checksum and Time-out errors)

— Classic or extended checksum calculation

— Configurable break duration of up to 50-bit times

— Programmable baud rate prescalers (13-bit mantissa, 4-bit fractional)

— Diagnostic features (Loop back, LIN bus stuck dominant detection)

— Interrupt driven operation with 16 interrupt sources

• LIN slave mode features

— Autonomous LIN header handling

— Autonomous LIN response handling

• UART mode

— Full-duplex operation

— Standard non return-to-zero (NRZ) mark/space format

— Data buffers with 4-byte receive, 4-byte transmit

— Configurable word length (8-bit, 9-bit, 16-bit, or 17-bit words)

— Configurable parity scheme: none, odd, even, always 0

— Speed as fast as 2 Mbit/s

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 17

— Error detection and flagging (Parity, Noise and Framing errors)

— Interrupt driven operation with four interrupt sources

— Separate transmitter and receiver CPU interrupt sources

— 16-bit programmable baud-rate modulus counter and 16-bit fractional

— Two receiver wake-up methods

• Support for DMA enabled transfers

1.5.29 Deserial Serial Peripheral Interface (DSPI)

The DSPI modules provide a synchronous serial interface for communication between the MPC5643L and external devices.

A DSPI module provides these features:

• Full duplex, synchronous transfers

• Master or slave operation

• Programmable master bit rates

• Programmable clock polarity and phase

• End-of-transmission interrupt flag

• Programmable transfer baud rate

• Programmable data frames from 4 to 16 bits

• As many as 8 chip select lines available, depending on package and pin multiplexing

• 4 clock and transfer attributes registers

• Chip select strobe available as alternate function on one of the chip select pins for de-glitching

• FIFOs for buffering as many as 5 transfers on the transmit and receive side

• Queueing operation possible through use of the eDMA

• General purpose I/O functionality on pins when not used for SPI

1.5.30 FlexPWM

The pulse width modulator module (FlexPWM) contains four PWM channels, each of which is configured to control a single

half-bridge power stage. Two modules are included on 257 MAPBGA devices; on the 144 LQFP package, only one module is

present. Additionally, four fault input channels are provided per FlexPWM module.

This PWM is capable of controlling most motor types, including:

• AC induction motors (ACIM)

• Permanent Magnet AC motors (PMAC)

• Brushless (BLDC) and brush DC motors (BDC)

• Switched (SRM) and variable reluctance motors (VRM)

• Stepper motors

A FlexPWM module implements the following features:

• 16 bits of resolution for center, edge aligned, and asymmetrical PWMs

• Maximum operating frequency as high as 120 MHz

— Clock source not modulated and independent from system clock (generated via secondary FMPLL)

• Fine granularity control for enhanced resolution of the PWM period

• PWM outputs can operate as complementary pairs or independent channels

• Ability to accept signed numbers for PWM generation

• Independent control of both edges of each PWM output

• Synchronization to external hardware or other PWM supported

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor18

• Double buffered PWM registers

— Integral reload rates from 1 to 16

— Half cycle reload capability

• Multiple ADC trigger events can be generated per PWM cycle via hardware

• Fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Independent top and bottom deadtime insertion

• Each complementary pair can operate with its own PWM frequency and deadtime values

• Individual software control for each PWM output

• All outputs can be forced to a value simultaneously

• PWMX pin can optionally output a third signal from each channel

• Channels not used for PWM generation can be used for buffered output compare functions

• Channels not used for PWM generation can be used for input capture functions

• Enhanced dual edge capture functionality

• Option to supply the source for each complementary PWM signal pair from any of the following:

— External digital pin

— Internal timer channel

— External ADC input, taking into account values set in ADC high- and low-limit registers

• DMA support

1.5.31 eTimer module

The MPC5643L provides three eTimer modules (on the LQFP package eTimer_2 is available internally only without any

external I/O access). Six 16-bit general purpose up/down timer/counters per module are implemented with the following

features:

• Maximum clock frequency of 120 MHz

• Individual channel capability

— Input capture trigger

— Output compare

— Double buffer (to capture rising edge and falling edge)

— Separate prescaler for each counter

— Selectable clock source

— 0–100% pulse measurement

— Rotation direction flag (Quad decoder mode)

• Maximum count rate

— Equals peripheral clock divided by 2 for external event counting

— Equals peripheral clock for internal clock counting

• Cascadeable counters

• Programmable count modulo

• Quadrature decode capabilities

• Counters can share available input pins

• Count once or repeatedly

• Preloadable counters

• Pins available as GPIO when timer functionality not in use

• DMA support

Introduction

MPC5643L Microcontroller Data Sheet, Rev. 9

Freescale Semiconductor 19

1.5.32 Sine Wave Generator (SWG)

A digital-to-analog converter is available to generate a sine wave based on 32 stored values for external devices (ex: resolver).

1.5.33 Analog-to-Digital Converter module (ADC)

The ADC module features include:

Analog part:

• 2 on-chip ADCs

— 12-bit resolution SAR architecture

— Same digital interface as in the MPC5604P family

— A/D Channels: 9 external, 3 internal and 4 shared with other A/D (total 16 channels)

— One channel dedicated to each T-sensor to enable temperature reading during application

— Separated reference for each ADC

— Shared analog supply voltage for both ADCs

— One sample and hold unit per ADC

— Adjustable sampling and conversion time

Digital part:

• 4 analog watchdogs comparing ADC results against predefined levels (low, high, range) before results are stored in

the appropriate ADC result location

• 2 modes of operation: CPU Mode or CTU Mode

• CPU mode features

— Register based interface with the CPU: one result register per channel

— ADC state machine managing three request flows: regular command, hardware injected command, software

injected command

— Selectable priority between software and hardware injected commands

— 4 analog watchdogs comparing ADC results against predefined levels (low, high, range)

— DMA compatible interface

• CTU mode features

— Triggered mode only

— 4 independent result queues (1  16 entries, 2  8 entries, 1  4 entries)

— Result alignment circuitry (left justified; right justified)

— 32-bit read mode allows to have channel ID on one of the 16-bit parts

— DMA compatible interfaces

• Built-in self-test features triggered by software

1.5.34 Cross Triggering Unit (CTU)

The ADC cross triggering unit allows automatic generation of ADC conversion requests on user selected conditions without

CPU load during the PWM period and with minimized CPU load for dynamic configuration.

The CTU implements the following features:

• Cross triggering between ADC, FlexPWM, eTimer, and external pins

• Double buffered trigger generation unit with as many as 8 independent triggers generated from external triggers

• Maximum operating frequency less than or equal to 120 MHz

• Trigger generation unit configurable in sequential mode or in triggered mode

• Trigger delay unit to compensate the delay of external low pass filter

MPC5643L Microcontroller Data Sheet, Rev. 9

Introduction

Freescale Semiconductor20

• Double buffered global trigger unit allowing eTimer synchronization and/or ADC command generation

• Double buffered ADC command list pointers to minimize ADC-trigger unit update

• Double buffered ADC conversion command list with as many as 24 ADC commands

• Each trigger capable of generating consecutive commands

• ADC conversion command allows control of ADC channel from each ADC, single or synchronous sampling,

independent result queue selection

• DMA support with safety features

1.5.35 Cyclic Redundancy Checker (CRC) Unit

The CRC module is a configurable multiple data flow unit to compute CRC signatures on data written to its input register.

The CRC unit has the following features:

• 3 sets of registers to allow 3 concurrent contexts with possibly different CRC computations, each with a selectable

polynomial and seed

• Computes 16- or 32-bit wide CRC on the fly (single-cycle computation) and stores result in internal register.

The following standard CRC polynomials are implemented:

—x

+ x

+ 1 [8-bit CRC]

—x

+ 1 [16-bit CRC-CCITT]

— x

+ x

+ x +1

[32-bit CRC-ethernet(32)]

• Key engine to be coupled with communication periphery where CRC application is added to allow implementation of

safe communication protocol

• Offloads core from cycle-consuming CRC and helps checking configuration signature for safe start-up or periodic

procedures

• CRC unit connected as peripheral bus on internal peripheral bus

• DMA support

1.5.36 Redundancy Control and Checker Unit (RCCU)

The RCCU checks all outputs of the sphere of replication (addresses, data, control signals). It has the following features:

• Duplicated module to guarantee highest possible diagnostic coverage (check of checker)

• Multiple times replicated IPs are used as checkers on the SoR outputs

1.5.37 Junction temperature sensor

The junction temperature sensor provides a value via an ADC channel that can be used by software to calculate the device

junction temperature.

The key parameters of the junction temperature sensor include:

• Nominal temperature range from –40 to 150 °C

• Software temperature alarm via analog ADC comparator possible

1.5.38 Nexus Port Controller (NPC)

The NPC module provides real-time development support capabilities for this device in compliance with the IEEE-ISTO

5001-2003. This development support is supplied for MCUs without requiring external address and data pins for internal

visibility.

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