SATA 2.0协议详解：修订1.0扩展与特性

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SATA 2.0协议是Serial ATA (串行高级硬盘接口)技术的一个重要升级版本，它在SATA 1.0的基础上进行了扩展和优化。发布于2002年10月16日，由APT Technologies、Dell Computer Corporation、Intel Corporation、Maxtor Corporation和Seagate Technology LLC等公司联合制定。这一规范的1.0修订版，也称为"Final Specification"，可以在www.serialata.org网站上获取。 SATA 2.0的主要改进点包括： 1. **带宽提升**：与SATA 1.0相比，SATA 2.0的最大数据传输速度翻了一番，达到了300MBps（兆比特每秒），比SATA 1.0的150MBps有了显著提高。这使得更快的数据读写成为可能，支持更高级别的存储设备性能。 2. **更高速的信号传输**：采用了更先进的信号处理技术和电缆设计，减少了串行数据传输中的延迟，提高了信号质量，从而实现更高的数据传输速率。 3. **支持热插拔和电源管理**：SATA 2.0继续支持热插拔功能，即在系统运行时可以安全地插入或移除硬盘，同时提升了电源管理能力，能够更有效地控制硬盘的功耗和休眠模式。 4. **错误检测和校验**：增强了错误检测和校验功能，提高了数据传输的可靠性，确保了数据的一致性和完整性。 5. **多任务处理能力**：SATA 2.0允许同时进行多个数据传输操作，提高了I/O性能，对于多任务环境下的应用有显著优势。 6. **向下兼容性**：尽管是新版本，但SATA 2.0仍然保持对SATA 1.0设备的兼容性，用户无需更换现有硬件就能享受到速度提升带来的好处。 7. **标准化和开放性**：SATA 2.0规范的发布进一步推动了硬盘接口的标准化进程，促进了不同厂商间产品的互换性和市场接受度。 8. **版权声明**：这个规范提供的是一种无保障的“原样提供”（As Is）资源，不包含任何形式的商业或法律保证，包括适销性、非侵权性和特定用途的适用性。所有作者免除关于使用或实施规范中信息可能侵犯任何专有权的责任，并明确指出提供此规范并不授予任何形式的知识产权许可。 SATA 2.0协议的出现不仅显著提高了硬盘接口的速度和效率，还为现代计算机系统提供了更好的性能基础，对于推动存储技术的发展起到了关键作用。随着技术的进步，SATA 3.0和后续版本进一步强化了这些优点，但SATA 2.0作为基础标准，其影响力至今仍不可忽视。

Type field value

(hex)

Assignment

Description

0x27 SATA 1.0

0x34 SATA 1.0

0x39 SATA 1.0

DMA Activate FIS – Device to host

0x41 SATA 1.0

DMA Setup FIS – Bi-directional

0x46 SATA 1.0

Data FIS – Bi-directional

0x58 SATA 1.0

BIST Activate FIS – Bi-directional

0x5F SATA 1.0

PIO Setup FIS – Device to host

0xA1 SATA 1.0

Set Device Bits FIS – Device to host

0xA6

Reserved for future Serial ATA definition

0xB8

Reserved for future Serial ATA definition

0xBF

Reserved for future Serial ATA definition

0xC7 SATA II

Vendor unique

0xD4 SATA II

Vendor unique

0xD9 SATA II Reserved for Serial ATA connectivity

expansion definition

Figure 8 FIS type value assignments

4. Command Layer

This section includes definitions of new command layer features and capabilities for the Serial

ATA specification. All new capabilities defined here are evolutionary, incremental, and optional

additions to the Serial ATA 1.0 specification.

4.1. Native Command Queuing

This section defines a simple and streamlined command queuing model for Serial ATA. The

command queuing model is derived in part from the legacy queuing definition but with some of

the legacy queuing aspects modified to take advantage of the capabilities of Serial ATA as well

as to streamline the overall mechanism. A race-free status return mechanism is defined that

minimizes the required protocol round trips in order to reduce the incurred overhead.

4.1.1. Goals, Objectives & Constraints

The native queuing definition has the following objectives and constraints:

- The queuing model must require no protocol additions or changes to the Serial ATA 1.0

specification in order to be implemented

- The queuing model must have minimal overhead in order to avoid potentially optimizing

the exceptional deeply-queued case at the expense of the typical lightly-queued case

- The impact to the HBA implementation must be minimized to avoid dramatic controller

redesign

- The software programming interface changes must be incremental to allow easy software

migration from existing ATA software drivers

This section is limited in scope to the interface between the device and the host controller and

does not define the host controller’s interface to host software. Native command queuing only

makes sense in the context of new driver software and therefore does not comprehend the needs

of master/slave emulation configurations that are used for supporting legacy software only.

4.1.2. Overview

The native queuing definition utilizes the reserved 32-bit field in the Set Device Bits FIS to convey

the pending status for each of up to 32 outstanding commands. The BSY bit in the Status register

conveys only the device’s readiness to receive another command, and does not convey the

completion status of queued commands. The 32 reserved bits in the Set Device Bits FIS are

handled as a 32-element array of active command bits (referred to as ACT bits), one for each

possible outstanding command, and the array is bit significant such that bit “n” in the array

corresponds to the pending status of the command with tag “n.”

Data returned by the device (or transferred to the device) for queued commands use the First

Party DMA mechanism to cause the host controller to select the appropriate destination/source

memory buffer for the transfer. The memory handle used for the buffer selection is the same as

the tag that is associated with the command. For traditional desktop host controllers, the handle

may be used to index into a vector of pointers to pre-constructed scatter/gather lists (often

referred to as physical region descriptor tables or simply PRD tables) in order to establish the

proper context in the host’s DMA engine.

Status is returned by updating the 32-element bit array in the Set Device Bits FIS for successful

completions. For failed commands, the device halts processing commands allowing host software

or controller firmware to intervene and resolve the source of the failure before processing is again

explicitly restarted.

4.1.3. Definition

4.1.3.1. Command Issue Mechanism

The Serial ATA transmission protocol is sensitive to the state of the BSY bit in the Status shadow

Shadow Register Block Registers can be safely written only when the BSY bit is cleared to zero,

the BSY bit conventions defined in Serial ATA 1.0 must be adhered to, and issuing a new

command shall only be attempted when the BSY bit is cleared to zero. When the BSY bit in the

Status shadow register is cleared to zero, another command may be issued to the device.

The state of the BSY bit in the Status shadow register shall be checked prior to attempting to

issue a new queued command. If the BSY bit is set to one, issuing the next command shall be

deferred until the BSY bit is cleared to zero. It is desirable to minimize such command issue

deferrals, so devices should clear the BSY bit to zero in a timely manner. Host controllers may

have internal designs that mitigate the need for host software to block on the state of the BSY bit.

The native queuing commands include a tag value that identifies the command. The tag value is

in the range 0 through 31 inclusive (the device queue depth is limited to 32 outstanding entries),

and is conveyed in the Register FIS when the command is issued. For devices that report

maximum queue depth less than 32 in their IDENTIFY DEVICE word 75, the host shall issue only

unique tag values that have a value less than the value reported. For example, for devices

reporting a maximum queue depth of 16, the host shall not issue a tag value greater than 15.

Upon issuing a new native queued command, the bit in the SActive register corresponding to the

tag value of the command being issued shall be set to one by the HBA prior to the command

being transmitted to the device. Section 5.1.1 describes the SActive register and the access

conventions for it.

4.1.3.2. Data Delivery Mechanism

The Serial ATA First Party DMA mechanism is used by the device to transmit (or receive) data for

an arbitrary queued command. The command’s tag value shall also be the DMA Buffer Identifier

used to uniquely identify the source/destination memory buffer for the transfer. The First Party

DMA mechanism defined in the Serial ATA 1.0 specification already specifies that the passed

buffer identifier is only a “token” and that it shall not be construed to be a physical address. Use of

the tag for the buffer identifier is therefore consistent with the existing Serial ATA specification.

The DMA Setup FIS is used by the device to select the proper transfer buffer prior to each data

transfer. Only a single DMA Setup FIS is required at the beginning of each transfer and if the

transfer spans multiple Data FISes a new DMA Setup FIS is not required before each Data FIS.

Serial ATA host controller hardware must account for the DMA Setup FIS buffer identifier being a

value between 0 and 31 and the host controller must select the proper transfer buffer based on

such an index.

For data transfers from the host to the device, an optimization to the First Party DMA mechanism

is included to eliminate one transaction by allowing the requested data to immediately be

transmitted to the device following such a request without the need for a subsequent DMA

Activate FIS for starting the flow of data. This optimization to the First Party DMA mechanism is

defined in section 3.1.

If non-zero buffer offsets in the DMA Setup FIS are not enabled (see section 4.3.4.1) or not

supported (see section 4.3.2), the data transfer for a command shall be satisfied to completion

following a DMA Setup FIS before data transfer for a different command may be started. Host

controllers are not required to preserve DMA engine context upon receipt of a new DMA Setup

FIS, and if non-zero buffer offsets are not enabled or not supported, it will not be possible for a

device to resume data transfer for a previously abandoned context at the point where it left off.

If the host controller hardware supports non-zero buffer offsets in the DMA Setup FIS and use of

non-zero offsets is enabled, the device may return data for a given command out of order (i.e.

returning data for the last half of the command first). In this case the device may also interleave

partial data delivery for multiple commands provided the device keeps track of the appropriate

buffer offsets. For example, data for the first half of command 0 may be delivered followed by

data for the first half of command 1 followed by the remaining data for command 0. By default use

of non-zero buffer offsets is disabled. See section 4.3.4.1 for information on enabling non-zero

buffer offsets for the DMA Setup FIS.

For selecting the memory buffer for data transfers, the DMA Setup FIS is issued by the device.

The DMA Setup FIS fields are defined in Figure 9 (see also the Serial ATA 1.0 specification).

Reserved (0) Reserved (0) A I D Reserved (0) FIS Type (41h)

0 TAG

Reserved (0)

DMA Buffer Offset

DMA Transfer Count

Reserved (0)

Figure 9 DMA Setup FIS definition for memory buffer selection

Field Definitions

FIS Type Set to a value of 41h. Defines the rest of the FIS fields. Defines the total length

of the FIS as seven Dwords.

D Indicates whether subsequent data transferred after this FIS is from transmitter to

receiver or from receiver to transmitter. Since the DMA Setup FIS is only issued

by the device for the queuing model defined here, the value in the field is defined

as 1 = device to host transfer (write to host memory), 0 = host to device transfer

(read from host memory).

A For a DMA Setup with transfer direction from host to device indicates whether the

host should immediately proceed with the data transfer without awaiting a

subsequent DMA Activate to start the transfer. See section 3.1 for details. For

DMA Setup with transfer direction from device to host, this bit shall be zero.

TAG This field is used to identify the DMA buffer region in host memory to select for

the data transfer. The low order 5 bits of the DMA Buffer Identifier Low field as

defined in the Serial ATA 1.0 specification shall be set to the TAG value

corresponding to the command TAG for which data is being transferred. The

remaining bits of the DMA Buffer Identifier Low/High shall be cleared to zero. The

64-bit Buffer Identifier field defined in the Serial ATA 1.0 specification is used to

convey a TAG value that occupies the five least-significant bits of the field.

DMA Buffer Offset

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