STM32F103C6低功耗32位微控制器数据手册

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"STM32F103C6是STMicroelectronics生产的基于ARM Cortex-M3内核的低密度性能线32位微控制器。这款芯片具有16KB或32KB的闪存以及6KB或10KB的SRAM。它支持USB、CAN接口，配备6个定时器，2个ADC和6个通信接口。" STM32F103C6的关键特性包括： 1. **高性能ARM Cortex-M3内核**：该微控制器搭载了运行频率高达72MHz的Cortex-M3处理器，提供1.25 DMIPS/MHz的性能（基于Dhrystone 2.1基准测试），并且在0等待状态内存访问下运行。内核还支持单周期乘法和硬件除法操作，提高了计算效率。 2. **存储器**：STM32F103C6有两种配置，分别带有16KB或32KB的闪存以及6KB或10KB的SRAM。闪存用于存储程序代码，SRAM则作为运行时的数据存储。 3. **时钟、复位和电源管理**：芯片可以在2.0V至3.6V的电压范围内工作，并且具备上电复位（POR）、掉电复位（PDR）以及可编程电压检测器（PVD）。还包括4到16MHz的晶体振荡器、8MHz的工厂校准内部RC振荡器和40kHz的内部RC振荡器。此外，还有一个为CPU时钟服务的锁相环（PLL）和为RTC（实时时钟）配备的32kHz振荡器。 4. **低功耗模式**：支持睡眠、停止和待机三种低功耗模式，以及VBAT电源，确保RTC和备份寄存器在主电源关闭时仍能工作。 5. **模拟功能**：拥有2个12位的A/D转换器，转换速度可达1微秒，最多可以处理16个通道。转换范围为0至3.6V，还配备了双采样保持功能和温度传感器。 6. **直接存储器访问（DMA）**：7通道DMA控制器支持定时器、ADC、SPIs、I2Cs和USARTs等外设，提高数据传输效率。 7. **通信接口**：包括USB接口和CAN总线，以及6个不同的通信接口，如SPI、I2C和USART，这些接口可以实现微控制器与各种外部设备之间的高效通信。 8. **其他功能**：除了上述特性，STM32F103C6还提供了丰富的GPIO端口、中断源和时基功能，使其适用于各种嵌入式应用，如工业控制、智能家居、物联网设备等。 STM32F103C6是一款功能强大的微控制器，集成了丰富的外设和通讯选项，适合于需要高效能、低功耗和多种接口功能的嵌入式设计。其紧凑的封装和广泛的电压范围使其在众多应用中具有高灵活性和适应性。

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Description STM32F103x4, STM32F103x6

16/99 DocID15060 Rev 7

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.6 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected

to the 16 external interrupt lines.

2.3.7 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Several prescalers allow the configuration of the AHB frequency, the high-speed APB

(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and

the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed

APB domain is 36 MHz. See

Figure 2 for details on the clock tree.

2.3.8 Boot modes

At startup, boot pins are used to select one of three boot options:

• Boot from User Flash

• Boot from System Memory

• Boot from embedded SRAM

The boot loader is located in System Memory. It is used to reprogram the Flash memory by

using USART1. For further details please refer to AN2606.

2.3.9 Power supply schemes

• V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs

and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC is used).

DDA

and V

SSA

must be connected to V

and V

, respectively.

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 11: Power supply scheme.

2.3.10 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

DocID15060 Rev 7 17/99

STM32F103x4, STM32F103x6 Description

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software.

Refer to Table 11: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.11 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop mode

• Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode, providing high

impedance output.

2.3.12 Low-power modes

The STM32F103xx performance line supports three low-power modes to achieve the best

compromise between low power consumption, short startup time and available wakeup

sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Stop mode

The Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

Description STM32F103x4, STM32F103x6

18/99 DocID15060 Rev 7

2.3.13 DMA

The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,

peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports

circular buffer management avoiding the generation of interrupts when the controller

reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and

advanced-control timers TIMx and ADC.

2.3.14 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are ten 16-bit

registers used to store 20 bytes of user application data when V

power is not present.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low-power RC oscillator or the high-speed external clock divided by 128. The

internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural crystal deviation. The RTC

features a 32-bit programmable counter for long-term measurement using the Compare

default configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.15 Timers and watchdogs

The low-density STM32F103xx performance line devices include an advanced-control

timer, two general-purpose timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the advanced-control and general-purpose timers.

Table 4. Timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM1 16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes 4 Yes

TIM2,

TIM3

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Yes 4 No

DocID15060 Rev 7 19/99

STM32F103x4, STM32F103x6 Description

Advanced-control timer (TIM1)

The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6

channels. It has complementary PWM outputs with programmable inserted dead-times. It

can also be seen as a complete general-purpose timer. The 4 independent channels can be

used for

• Input capture

• Output compare

• PWM generation (edge- or center-aligned modes)

• One-pulse mode output

If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to two synchronizable general-purpose timers embedded in the STM32F103xx

performance line devices. These timers are based on a 16-bit auto-reload up/down counter,

a 16-bit prescaler and feature 4 independent channels each for input capture/output

compare, PWM or one-pulse mode output. This gives up to 12 input captures/output

compares/PWMs on the largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently of the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free-running timer for application timeout

management. It is hardware- or software-configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

the main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

Description STM32F103x4, STM32F103x6

20/99 DocID15060 Rev 7

SysTick timer

This timer is dedicated for OS, but could also be used as a standard downcounter. It

features:

• A 24-bit downcounter

• Autoreload capability

• Maskable system interrupt generation when the counter reaches 0

• Programmable clock source

2.3.16 I²C bus

The I²C bus interface can operate in multimaster and slave modes. It can support standard

and fast modes.

It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode.

A hardware CRC generation/verification is embedded.

It can be served by DMA and they support SM Bus 2.0/PM Bus.

2.3.17 Universal synchronous/asynchronous receiver transmitter (USART)

One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The

other available interface communicates at up to 2.25 Mbit/s. They provide hardware

management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816

compliant and have LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

2.3.18 Serial peripheral interface (SPI)

The SPI interface is able to communicate up to 18 Mbits/s in slave and master modes in full-

duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

The SPI interface can be served by the DMA controller.

2.3.19 Controller area network (CAN)

The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It

can receive and transmit standard frames with 11-bit identifiers as well as extended frames

with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and

14 scalable filter banks.

2.3.20 Universal serial bus (USB)

The STM32F103xx performance line embeds a USB device peripheral compatible with the

USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function

interface. It has software-configurable endpoint setting and suspend/resume support. The

dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use

a HSE crystal oscillator).

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