0.55V超低功耗CMOS Sub-BGR：28ppm/°C高精度与83nW设计

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本文档主要探讨了一项针对低电压自供电设备的创新设计——一款具有超低功耗曲率补偿的0.55伏特、28毫珀尔摄氏度（ppm/°C）、仅83纳瓦特（nW）的CMOS亚带隙基准电压参考电路（Sub-BGR）。在当今电子设备对能源效率日益增长的需求下，这项研究对于延长电池寿命、提升便携式设备性能具有重要意义。设计的核心亮点是提出了一种新型的超低功耗曲率补偿电路，旨在优化温度系数（TC），使其在宽温范围内保持高精度。传统的电路设计往往受到温度变化的影响，而这种新电路通过减小温度变化对基准电压输出的影响，显著提高了电路的稳定性。为了进一步降低功耗并减少开关活动对电路的干扰，如时钟馈通和充电注入，作者设计了一个时钟缩放电路。这个电路有效地降低了线路敏感性（LS），即电路对电源电压波动的响应，从而增强了电路的抗干扰能力。该亚带隙基准电压参考电路采用的是0.18微米标准CMOS工艺进行实现，其总面积仅为0.061平方毫米，显示出极高的集成度。经过30个芯片的实际测量，当工作电压为0.55伏特，环境温度为27摄氏度时，平均功耗仅为83纳瓦特。在0.55到1伏特的供电电压范围内，温度系数仅为0.059%每伏特（V/°C），并且经过调整后，误差控制在±0.75%（3σ），表现出极高的精度和稳定性。这项研究成果对于设计低功耗、高性能的微电子设备具有实际应用价值，特别是在物联网（IoT）设备、无线传感器网络（WSN）以及电池供电的移动设备中，能有效降低能耗，延长电池寿命，同时保证了电路在各种环境条件下的可靠性能。这是一项在电源管理领域具有创新性和实用性的研究。

LIU et al.: 0.55-V, 28-ppm/

◦

C, 83-nW CMOS SUB-BGR WITH ULTRALOW POWER CURVATURE COMPENSATION 97

Fig. 4. (a) Clock scaling down circuit. (b) The control signal of the clock

scaling down circuit.

component. In our design, V

HOLD

is K×V

, and it is between

120 mV and 240 mV under temperature variations. Thus, the

modiﬁed switch has a 50% lower leakage current compared

with the previous low leakage current switch at 120 °C.

Additionally, the error on the output of the divider, caused

by the leakage current, is reduced by 50%.

Another effect is the clock feedthrough and charge injection,

which only cause a constant error if the clock amplitude is

constant. However, when the supply voltage ﬂuctuates, this

error is no longer constant and will deteriorate the precision

of K×V

, resulting in poor line sensitivity (LS). In previ-

ous work [16], this effect was minimized by using dummy

MOSFETs, but this solution suffers from transistor mis-

match. In this paper, we solve this problem by restricting

the clock amplitude. Fig. 4 (a) shows the clock scaling down

circuit, and Fig. 4 (b) shows the control signal. We use 2×V

as the supply voltage of the control signal in the switches.

As a result, when the supply voltage ﬂuctuates, the clock

feedthrough and charge injection only cause a constant error.

Since the driving capability of 2×V

is weak, clocks A and B

are not in phase, which prevents the pulse current from 2×V

to GND.

The SC V

divider with improved switches and the time

sequence of the control signals are shown in Fig. 5. The low

voltage oscillator provides a clock of 200 KHz for the control

signals. To reduce the power consumption of the SC divider, a

16-frequency-divider is used to reduce the operation frequency.

The R-C delay network and logic circuit are used to generate

the multi-phase control signals. The clock bootstrap [27] can

boost the amplitude of the control signal to 2×VDD.

There are 3 phases for the SC V

divider. In the ﬁrst

phase, switches S1 and S3 are on, and V

is sampled

by C1. In the second phase, only switch S2 is on, and

C1 and C2 generate K(=C1/(C1+C2))×V

. In the third

phase, switches S2 and S4 are on. In this phase, C1 and C2

work as a voltage source to charge C3. After several cycles,

the voltage across C3 is equal to K×V

. The clock signals A

and A

dum

,BandB

dum

,CandC

dum

are two-phase non-overlap

clocks. As long as the switches are off, the ampliﬁer’s output is

connected to the source or drain to reduce the leakage current.

A single stage ampliﬁer with a PMOS input pair is used in the

divider, and the current consumption is approximately 2.5 nA.

C. Trimmable PTAT Voltage Generator

The SC V

divider generates a high precision K×V

This K×V

should be added to the PTAT voltage to generate

a reference voltage. In this paper, to generate the PTAT

voltage, we use the circuit from [28]. This PTAT voltage is

generated by using the offset of an ampliﬁer to avoid a large

resistor. By setting the input pair or the current mirror in the

ampliﬁer to be different, the PTAT voltage is generated at

the two inputs of the ampliﬁer. To compensate for K×V

a 3-stage PTAT voltage generator is used, as shown in Fig. 6.

Therefore, the output reference voltage is

REF_NC

= K × V

+ η × V

× ln(k

× k

)

= K × V

+ η × V

× ln

(

)

(3)

where k

is the width ratio of P8 and P7, k

is the width

ratio of P10 and P9, k

is width ratio of P12 and P11, and

= k

×k

.TheV

REF_NC

has a large TC due to the lack

of curvature compensation. Thus, it is not suitable for high

precision applications. Figure 7 shows the simulation result

for voltage, V

REF_NC

, versus temperature. V

REF_NC

varies by

approximately 3.5 mV at a temperature range of −45 °C to

120 °C and its calculated TC is approximately 48 ppm/°C.

The accuracy of K×V

across the process variations is

relatively high. However, there is an error that mainly comes

from the offset voltage in the PTAT generator because the

mismatch is large. As shown in Fig. 6, a 3-bit trimming

circuit with a 3.25 mV average step was adopted to improve

the precision of the PTAT voltage. The 3-bit trimming is

realized by controlling the transistors, PM

− PM

,which

can change coefﬁcients k

to k

in (3). In this design example,

the default trimming code is 100 for generating 461 mV of

reference voltage. Fig. 7 also shows the reference voltage when

the trimming code varies from 000 to 111. The trimming step

is not constant because the reference voltage is non-linear

under the control of k

− k

. However, the variation in the

trimming step can be reduced by choosing a proper transistor

size.

To improve the line sensitivity of the reference, the bias

current should also have low line sensitivity. Fig. 8 shows the

low voltage current source and the current mirror [27]. All of

the transistors work in the subthreshold region, and the current

ﬂowing through resistor R

is a PTAT current as

× ln(n)

(4)

where n is the size ratio of PM1 and PM2. A low voltage

ampliﬁer consisting of PM3, PM4, NM3 and NM4 is used

to clamp the drain voltage of NM1 and NM2. It can reduce

the inﬂuence of the channel length modulation in NM1 and

NM2, and improve the line sensitivity of the current source.

The current mirror, which is powered by 2×VDD, is used to

generate the global bias voltages, VB1 and VB2, for the entire

circuit.

III. L

OW POWER CURVATURE COMPENSATION

A. Proposed Low Power Curvature Compensation

In recent years, several low power voltage references have

been published [6]–[10], [27], [28]. These voltage references

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