MIPS32 24KEc处理器核心：高性能低功耗RISC内核

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"MIPS32 24KEc处理器核心数据手册" MIPS32 24KEc处理器核心是一款由MIPS Technologies Inc.设计的高性能、低功耗32位MIPS RISC（精简指令集计算）核心，特别针对定制硅片上的系统应用。该核心适用于半导体制造商、ASIC开发者以及希望快速将自定义逻辑和外围设备与高性能RISC处理器集成的系统原始设备制造商。其完全可综合，并且高度跨工艺平台移植，能轻松融入全面的系统级芯片设计中，使开发者能够专注于最终用户产品。 24KEc核心实现了MIPS32 Release 2架构，采用8级流水线设计。它支持MIPS16e应用特定扩展以及32位特权资源架构。这种标准架构确保了广泛的工业标准工具和开发系统的兼容性。 24KEc核心集成了DSP（数字信号处理）应用特定扩展（ASE），提供了增强的计算能力，特别适合需要高效处理数字信号处理任务的场合。这包括对快速乘法和向量操作的支持，使得该核心在音频、视频编码和解码、图像处理以及通信等领域表现出色。此外，24KEc核心还具有节能特性，如动态电压频率调整（DVFS）和低功耗模式，这些功能有助于降低整体系统能耗，适应各种功耗敏感的应用场景。其微架构优化了指令执行效率，通过分支预测和高速缓存机制减少延迟，提高了处理器的吞吐量和响应速度。该核心的可定制性是其一大亮点，允许开发者根据具体需求调整和扩展硬件接口，以满足特定应用的需求。同时，由于遵循MIPS32架构，开发者可以利用丰富的MIPS生态系统，包括编译器、调试工具、操作系统和中间件等，加速软件开发进程。 MIPS32 24KEc处理器核心是面向嵌入式和物联网领域的强大解决方案，它的高性能、低功耗特性和广泛的工具支持使其成为实现高效能、低功耗系统设计的理想选择。对于那些寻求快速产品上市并需要在资源受限环境中运行复杂算法的开发者来说，24KEc核心是一个极具吸引力的选择。

MIPS32® 24KEc™ Processor Core Datasheet, Revision 01.02 11

per-page granularity. The 24KEc implementation

allows a wide range of page sizes to be present

simultaneously.

2. Fixed Mapping Translation (FMT) -style MMU. The

FMT is much simpler and smaller than the TLB-style

MMU, and is a good choice when the full protection

and ﬂexibility of the TLB is not needed.

Translation Lookaside Buffer (TLB)

The TLB consists of three address translation buffers:

• 16/32/64 dual-entry fully associative Joint TLB (JTLB)

• 4-entry fully associative Instruction Micro TLB (ITLB)

• 8-entry fully associative Data Micro TLB (DTLB)

When an instruction or data address is calculated, the

virtual address is compared to the contents of the

appropriate micro TLB (uTLB). If the address is not found

in the ITLB or DTLB, the JTLB is accessed. If the entry is

found in the JTLB, that entry is then written into the uTLB.

If the address is not found in the JTLB, a TLB exception is

taken.

Figure 4 shows how the ITLB, DTLB, and JTLB are

implemented in the 24KEc core.

Figure 4 Address Translation During a Cache Access

Joint TLB (JTLB)

The 24KEc core implements a fully associative JTLB

containing 16, 32, or 64-dual-entries mapping up to 128

virtual pages to their corresponding physical addresses.

The purpose of the TLB is to translate virtual addresses and

their corresponding ASIDs into a physical memory

address. The translation is performed by comparing the

upper bits of the virtual address (along with the ASID)

against each of the entries in the tag portion of the joint

TLB structure.

The JTLB is organized as pairs of even and odd entries

containing pages that range in size from 4 KB to 256 MB,

in factors of four, into the 4 GB physical address space. The

JTLB is organized in page pairs to minimize the overall

size. Each tag entry corresponds to two data entries: an

even page entry and an odd page entry. The highest order

virtual address bit not participating in the tag comparison is

used to determine which of the data entries is used. Since

page size can vary on a page-pair basis, the determination

of which address bits participate in the comparison and

which bit is used to make the even-odd determination is

decided dynamically during the TLB look-up.

Instruction TLB (ITLB)

The ITLB is a small 4-entry, fully associative TLB

dedicated to performing translations for the instruction

stream. The ITLB only maps 4 KB or 1 MB pages/

subpages. For 4 KB or 1 MB pages, the entire page is

mapped in the ITLB. If the main TLB page size is between

4 KB and 1 MB, only the current 4 KB subpage is mapped.

Similarly, for page sizes larger than 1 MB, the current 1

MB subpage is mapped.

The ITLB is managed by hardware and is transparent to

software. The larger JTLB is used as a backing structure for

the ITLB. If a fetch address cannot be translated by the

ITLB, the JTLB is used to attempt to translate it in the

following clock cycle, or when available. If successful, the

translation information is copied into the ITLB for future

use. There is a minimum two cycle ITLB miss penalty.

Data TLB (DTLB)

The DTLB is a small 8-entry, fully associative TLB

dedicated to performing translations for loads and stores.

Similar to the ITLB, the DTLB only maps either 4 KB or 1

MB pages/subpages.

The DTLB is managed by hardware and is transparent to

software. The larger JTLB is used as a backing structure for

the DTLB. If a load/store address cannot be translated by

the DTLB, a lookup is done in the JTLB. If the JTLB

translation is successful, the translation information is

copied into the DTLB for future use. The DTLB miss

penalty is also two cycles.

Instruction

Address

Calculator

ITLB

DTLB

Data

Address

Calculator

Comparator

Instruction

Cache

Tag RAM

Data

Cache

TagRAM

Virtual Address

Instruction

Hit/Miss

Data

Hit/Miss

JTLB

IVA

Entry

DVA

12 MIPS32® 24KEc™ Processor Core Datasheet, Revision 01.02

Figure 5 32-bit Virtual Address Translation

Virtual-to-Physical Address Translation

Converting a virtual address to a physical address begins by

comparing the virtual address from the processor with the

virtual addresses in the TLB; there is a match when the

virtual page number (VPN) of the address is the same as the

VPN ﬁeld of the entry, and either:

• The Global (G) bit of the TLB entry is set, or

• The ASID ﬁeld of the virtual address is the same as the

ASID ﬁeld of the TLB entry.

This match is referred to as a TLB hit. If there is no match,

a TLB miss exception is taken by the processor and

software is allowed to reﬁll the TLB from a page table of

virtual/physical addresses in memory.

Figure 5 shows a ﬂow diagram of the address translation

process for two different page sizes.

The top portion of Figure 5 shows a virtual address for a 4

KB page size. The width of the Offset in Figure 5 is deﬁned

by the page size. The remaining 20 bits of the address

represent the virtual page number (VPN), and index the

1M-entry page table.

The bottom portion of Figure 5 shows the virtual address

for a 16 MB page size. The remaining 8 bits of the address

represent the VPN, and index the 256-entry page table.

In Figure 5, the virtual address is extended with an 8-bit

address space identiﬁer (ASID), which reduces the

frequency of TLB ﬂushes during context switches. This 8-

bit ASID contains the number assigned to that process and

is stored in the CP0 EntryHi register.

Hits, Misses, and Multiple Matches

Each JTLB entry contains a tag portion and a data portion.

If a match is found, the upper bits of the virtual address are

replaced with the page frame number (PFN) stored in the

corresponding entry in the data array of the joint TLB

(JTLB). The granularity of JTLB mappings is deﬁned in

terms of TLB pages. The 24KEc core’s JTLB supports

pages of different sizes ranging from 4 KB to 256 MB in

factors of 4.

Table 5 shows the address bits used for even/odd bank

selection depending on page size and the relationship

between the legal values in the mask register and the

selected page size.

11 0

20 12

VPN Offset

3239

ASID

Virtual Address with 1M (2

) 4 KB pages

8 24

Offset

Virtual Address with 256 (2

)16 MB pages

8 bits = 256 pages

20 bits = 1M pages

ASID

VPN

Virtual-to-physical

translation in TLB

Bit 31 of the virtual

address selects user and

kernel address spaces

Offset passed unchanged to

physical memory

Virtual-to-physical

translation in TLB

TLB

PFN

Offset

Offset passed unchanged

to physical memory

32-bit Physical Address

MIPS32® 24KEc™ Processor Core Datasheet, Revision 01.02 13

If no match occurs (TLB miss), an exception is taken and

software reﬁlls the TLB from the page table resident in

memory. Software can write over a selected TLB entry or

use a hardware mechanism to write into a random entry.

The 24KEc core implements a TLB write compare

mechanism to ensure that multiple TLB matches do not

occur. On the TLB write operation, the write value is

compared with all other entries in the TLB. If a match

occurs, the 24KEc core takes a machine check exception,

sets the TS bit in the CP0 Status register, and aborts the

write operation.

Compared with previous cores from MIPS Technologies,

the 24KEc core uses a more relaxed check for multiple

matches in order to avoid machine check exceptions while

ﬂushing or initializing the TLB. On a write, all matching

entries are disabled to prevent them from matching on

future compares. A machine check is only signaled if the

entry being written has its valid bit set, the matching entry

in the TLB has its valid bit set, and the matching entry is

not the entry being written.

TLB Tag and Data Formats

Figure 6 shows the format of a TLB tag entry. The entry is

divided into the follow ﬁelds:

• Global process indicator

• Address space identiﬁer

• Virtual page number

• Compressed page mask

Setting the global process indicator (G bit) indicates that

the entry is global to all processes and/or threads in the

system. In this case, the 8-bit address space identiﬁer

(ASID) value is ignored since the entry is not relative to a

speciﬁc thread or process.

The ASID ﬁeld can help to reduce the frequency of TLB

ﬂushes on a context switches. The existence of the ASID

allows multiple processes to exist in both the TLB and

instruction caches. The current ASID value is stored in the

EntryHi register and is compared to the ASID value of each

entry. Figure 6 and Table 6 show the TLB tag entry format.

Figure 6 TLB Tag Entry Format

Figure 7 and Table 7 show the TLB data array entry format.

Table 5 Mask and Page Size Values

Pagemask[28:13] Page Size

Even/Odd Bank

Select Bit

0000000000000000 4KB VAddr[12]

0000000000000011 16KB VAddr[14]

0000000000001111 64KB VAddr[16]

0000000000111111 256KB VAddr[18]

0000000011111111 1MB VAddr[20]

0000001111111111 4MB VAddr[22]

0000111111111111 16MB VAddr[24]

0011111111111111 64MB VAddr[26]

1111111111111111 256MB VAddr[28]

Table 6 TLB Tag Entry Fields

Field Name Description

Global Bit. When set, indicates that this

entry is global to all processes and/or

threads and thus disables inclusion of the

ASID in the comparison.

ASID[7:0]

Address Space Identiﬁer. Identiﬁes with

which process or thread this TLB entry is

associated.

VPN2[31:29],

VPN2[28:13]

Virtual Page Number divided by 2. This

ﬁeld contains the upper bits of the virtual

page number. Because it represents a pair

of TLB pages, it is divided by 2. Bits 31:29

are always included in the TLB lookup

comparison. Bits 28:13 are included

depending on the page size.

CMASK[8:0]

Compressed page mask value. This ﬁeld is

a compressed version of the page mask. It

deﬁnes the page size by masking the

appropriate VPN2 bits from being involved

comparison. It is also used to determine

which address bit is used to make the even-

odd page determination.

G ASID[7:0] VPN2[31:29] VPN2[28:11] CMASK[8:0]

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