"DS90UH926Q-Q1 FPD-Link解串器与RGB数字显示接口详解"
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更新于2023-12-20
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The TI-DS90UH926Q-Q1.pdf is a technical document that describes the features and specifications of the FPD-Link III serializer and deserializer (SerDes) for RGB digital display interfaces. The document provides detailed information about the functionality and usage of the DS90UH926Q, including its compatibility with the DS90UH925Q and its support for 720p resolution and 24-bit color depth.
The FPD-Link III SerDes is designed to transmit high-speed digital video data over a single twisted pair cable, making it ideal for automotive and industrial applications where space and weight are limited. The DS90UH926Q supports AC-coupled transmission over 100-ohm shielded twisted pair (STP) cables, providing robust and reliable communication between the host graphics processor and the display.
The document outlines the pinout and configuration of the DS90UH926Q, including the various control signals and data lanes for transmitting RGB, audio, and other auxiliary data. It also discusses the power supply requirements and voltage levels for the different I/O interfaces, ensuring proper operation and signal integrity in a variety of system designs.
In addition to the technical details, the document provides links to product folders, ordering information, and other related resources for customers and developers interested in incorporating the DS90UH926Q into their designs. It also highlights the availability of technical documents and tools to assist in the evaluation, testing, and integration of the SerDes into specific application scenarios.
Overall, the TI-DS90UH926Q-Q1.pdf serves as a comprehensive reference for understanding the capabilities and specifications of the DS90UH926Q FPD-Link III serializer and deserializer, making it a valuable resource for engineers and designers working on display and video interface solutions in automotive and industrial settings.
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DS90UH926Q-Q1
www.ti.com.cn
ZHCSAP4M –OCTOBER 2010–REVISED AUGUST 2017
Copyright © 2010–2017, Texas Instruments Incorporated
6.8 Recommended Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
MIN NOM MAX UNIT
f
SCL
SCL Clock Frequency
Standard Mode 0 100 kHz
Fast Mode 0 400 kHz
t
LOW
SCL Low Period
Standard Mode 4.7 µs
Fast Mode 1.3 µs
t
HIGH
SCL High Period
Standard Mode 4 µs
Fast Mode 0.6 µs
t
HD;STA
Hold time for a start or a
repeated start condition
Figure 9
Standard Mode 4 µs
Fast Mode 0.6 µs
t
SU:STA
Setup time for a start or a
repeated start condition
Figure 9
Standard Mode 4.7 µs
Fast Mode 0.6 µs
t
HD;DAT
Data Hold Time
Figure 9
Standard Mode 0 3.45 µs
Fast Mode 0 0.9 µs
t
SU;DAT
Data Setup Time
Figure 9
Standard Mode 250 ns
Fast Mode 100 ns
t
SU;STO
Setup Time for STOP
Condition, Figure 9
Standard Mode 4 µs
Fast Mode 0.6 µs
t
BUF
Bus Free Time
Between STOP and START,
Figure 9
Standard Mode 4.7 µs
Fast Mode 1.3 µs
t
r
SCL and SDA Rise Time,
Figure 9
Standard Mode 1000 ns
Fast Mode 300 ns
t
f
SCL and SDA Fall Time,
Figure 9
Standard Mode 300 ns
Fast mode 300 ns
6.9 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS PIN/FREQ. MIN TYP MAX UNIT
t
RCP
PCLK Output Period t
RCP
= t
TCP
PCLK
11.76 T 200 ns
t
RDC
PCLK Output Duty Cycle 45% 50% 55%
t
CLH
LVCMOS Low-to-High Transition
Time
Figure 3
V
DDIO
= 1.71 to 1.89 V,
C
L
= 12 pF
R[7:0], G[7:0],
B[7:0], HS,
VS, DE,
PCLK, LOCK,
PASS, MCLK,
I2S_CLK,
I2S_WC,
I2S_DA,
I2S_DB
2 3 ns
V
DDIO
= 3 to 3.6 V,
C
L
= 12 pF
2 3 ns
t
CHL
LVCMOS High-to-Low Transition
Time
Figure 3
V
DDIO
= 1.71 to 1.89 V,
C
L
= 12 pF
2 3 ns
V
DDIO
= 3 to 3.6 V,
C
L
= 12 pF
2 3 ns
t
ROS
Data Valid before PCLK – Setup
Time
SSCG = OFF
Figure 6
V
DDIO
= 1.71 to 1.89 V,
C
L
= 12 pF
2.2 ns
V
DDIO
= 3 to 3.6 V,
C
L
= 12 pF
2.2 ns
t
ROH
Data Valid after PCLK – Hold
Time
SSCG = OFF
Figure 6
V
DDIO
= 1.71 to 1.89 V,
C
L
= 12 pF
3 ns
V
DDIO
= 3 to 3.6 V,
C
L
= 12 pF
3 ns
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