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S32K14X系列芯片安全手册与参考资源
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更新于2024-07-18
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本文档是关于NXP公司的S32K14X系列微控制器的手册,该系列芯片设计遵循ISO 26262标准,旨在实现ASIL-B级别的功能安全。手册包括了编程模型、功能描述、操作条件、电气特性、安全概念以及动态FMEDA分析,以支持在安全相关系统中集成S32K14X芯片。S32K14X系列是NXP的SafeAssure解决方案的一部分,提供了全面的功能安全支持。
S32K14X系列参考手册详细介绍了该系列MCU的功能和用法。手册分为多个章节,包括:
1. 关于本手册:
- 描述了手册的目标读者,组织结构,以及如何找到与特定芯片相关的具体信息。
- 注释、警告和注意事项的使用规范,以及数字系统、排版表示和专业术语的解释。
2. 引言:
- 提供了S32K14X系列的概述,介绍了其主要特点和功能。
- 通过块图展示了芯片内部结构,以及不同型号间的特性对比。
- 详细列出了应用领域,如汽车电子、工业控制等。
- 分类了模块功能,包括ARM Cortex-M4F核心模块、系统模块、内存和内存接口、电源管理、时钟和模拟模块等。
其中,S32K14X的特色在于其内置的安全概念,这些概念在安全手册(S32K14xSM)中详细阐述,涵盖了芯片内的安全机制、系统级硬件和软件的安全措施,以及减少依赖性故障的策略。数据表(S32K14x)则包含了芯片的操作条件、时序和电气特性。
动态FMEDA(故障模式、效应和诊断分析)提供了定制系统级安全机制的能力,包括针对ISO 26262的SPFM、LFM和PMHF指标,以及IEC 61508的SFF和Beta IC Factor。FMEDA报告详细描述了分析方法、支持的安全机制、故障率来源、故障模式以及分析假设。
S32K14X系列是为需要高度安全性能的应用而设计的微控制器,适用于需要满足严格功能安全标准的项目,如汽车电子系统。通过提供的参考手册、数据表、安全手册和FMEDA报告,开发者可以全面理解和利用S32K14X系列的潜力,以构建符合ASIL-B标准的安全相关系统。对于更多关于NXP的功能安全信息,可以通过访问NXP的SafeAssure网站获取。
Section number Title Page
25.3 Clock definitions...........................................................................................................................................................502
25.4 Internal clocking requirements..................................................................................................................................... 504
25.4.1 Clock divider values after reset......................................................................................................................507
25.4.2 HSRUN mode clocking................................................................................................................................. 507
25.4.3 VLPR mode clocking.....................................................................................................................................507
25.5 Clock Gating.................................................................................................................................................................508
25.6 Module clocks...............................................................................................................................................................508
Chapter 26
System Clock Generator (SCG)
26.1 Chip-specific SCG information.................................................................................................................................... 519
26.1.1 SCG chip-specific register configuration.......................................................................................................519
26.1.2 SOSCCFG[RANGE] description...................................................................................................................519
26.1.3 Oscillator restrictions..................................................................................................................................... 519
26.2 Introduction...................................................................................................................................................................520
26.2.1 Features.......................................................................................................................................................... 520
26.3 Memory Map/Register Definition.................................................................................................................................521
26.3.1 Version ID Register (SCG_VERID)..............................................................................................................522
26.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 523
26.3.3 Clock Status Register (SCG_CSR)................................................................................................................523
26.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................526
26.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................528
26.3.6 HSRUN Clock Control Register (SCG_HCCR)............................................................................................530
26.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................532
26.3.8 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................534
26.3.9 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 536
26.3.10 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 537
26.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................539
26.3.12 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 540
26.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................541
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Section number Title Page
26.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 542
26.3.15 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................544
26.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 545
26.3.17 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)..........................................................................545
26.3.18 Fast IRC Status Register (SCG_FIRCSTAT)................................................................................................547
26.3.19 System PLL Control Status Register (SCG_SPLLCSR)............................................................................... 548
26.3.20 System PLL Divide Register (SCG_SPLLDIV)............................................................................................550
26.3.21 System PLL Configuration Register (SCG_SPLLCFG)............................................................................... 551
26.4 Functional description...................................................................................................................................................552
26.4.1 SCG Clock Mode Transitions........................................................................................................................552
Chapter 27
Peripheral Clock Controller (PCC)
27.1 Chip-specific PCC information.....................................................................................................................................555
27.2 Introduction...................................................................................................................................................................555
27.3 Features.........................................................................................................................................................................555
27.4 Functional description...................................................................................................................................................556
27.5 Memory map and register definition.............................................................................................................................557
27.6 PCC Register Descriptions........................................................................................................................................... 557
27.6.1 PCC Memory Map.........................................................................................................................................557
27.6.2 PCC FTFC Register (PCC_FTFC)................................................................................................................ 558
27.6.3 PCC DMAMUX Register (PCC_DMAMUX).............................................................................................. 559
27.6.4 PCC FlexCAN0 Register (PCC_FlexCAN0)................................................................................................ 561
27.6.5 PCC FlexCAN1 Register (PCC_FlexCAN1)................................................................................................ 562
27.6.6 PCC FTM3 Register (PCC_FTM3)............................................................................................................... 563
27.6.7 PCC ADC1 Register (PCC_ADC1)...............................................................................................................565
27.6.8 PCC FlexCAN2 Register (PCC_FlexCAN2)................................................................................................ 566
27.6.9 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................568
27.6.10 PCC LPSPI1 Register (PCC_LPSPI1)...........................................................................................................569
27.6.11 PCC LPSPI2 Register (PCC_LPSPI2)...........................................................................................................571
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Section number Title Page
27.6.12 PCC PDB1 Register (PCC_PDB1)................................................................................................................572
27.6.13 PCC CRC Register (PCC_CRC)....................................................................................................................573
27.6.14 PCC PDB0 Register (PCC_PDB0)................................................................................................................575
27.6.15 PCC LPIT Register (PCC_LPIT)...................................................................................................................576
27.6.16 PCC FTM0 Register (PCC_FTM0)............................................................................................................... 578
27.6.17 PCC FTM1 Register (PCC_FTM1)............................................................................................................... 579
27.6.18 PCC FTM2 Register (PCC_FTM2)............................................................................................................... 581
27.6.19 PCC ADC0 Register (PCC_ADC0)...............................................................................................................582
27.6.20 PCC RTC Register (PCC_RTC)....................................................................................................................584
27.6.21 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................585
27.6.22 PCC PORTA Register (PCC_PORTA)......................................................................................................... 587
27.6.23 PCC PORTB Register (PCC_PORTB)..........................................................................................................588
27.6.24 PCC PORTC Register (PCC_PORTC)..........................................................................................................589
27.6.25 PCC PORTD Register (PCC_PORTD)......................................................................................................... 591
27.6.26 PCC PORTE Register (PCC_PORTE).......................................................................................................... 592
27.6.27 PCC FlexIO Register (PCC_FlexIO).............................................................................................................593
27.6.28 PCC EWM Register (PCC_EWM)................................................................................................................595
27.6.29 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 596
27.6.30 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 598
27.6.31 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 599
27.6.32 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 601
27.6.33 PCC CMP0 Register (PCC_CMP0)...............................................................................................................602
Chapter 28
Memories and Memory Interfaces
28.1 Introduction...................................................................................................................................................................605
28.2 Flash Memory Controller and flash memory modules................................................................................................. 605
28.3 SRAM configuration.....................................................................................................................................................605
28.3.1 SRAM sizes....................................................................................................................................................606
28.3.2 SRAM accessibility........................................................................................................................................606
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28.3.3 SRAM arbitration and priority control...........................................................................................................608
28.3.4 SRAM retention: power modes and resets.....................................................................................................608
Chapter 29
Local Memory Controller (LMEM)
29.1 Chip-specific LMEM information................................................................................................................................ 609
29.1.1 LMEM region description..............................................................................................................................609
29.1.2 LMEM SRAM size........................................................................................................................................ 609
29.2 Introduction...................................................................................................................................................................609
29.2.1 Block Diagram............................................................................................................................................... 609
29.2.2 Cache features................................................................................................................................................611
29.3 Memory Map/Register Definition.................................................................................................................................612
29.3.1 LMEM Register Descriptions........................................................................................................................ 612
29.4 Functional Description..................................................................................................................................................621
29.4.1 LMEM Function............................................................................................................................................ 622
29.4.2 SRAM Function............................................................................................................................................. 622
29.4.3 Cache Function.............................................................................................................................................. 624
29.4.4 Cache Control................................................................................................................................................ 625
Chapter 30
Miscellaneous System Control Module (MSCM)
30.1 Chip-specific MSCM information................................................................................................................................631
30.2 Overview.......................................................................................................................................................................631
30.3 Chip Configuration and Boot........................................................................................................................................631
30.4 MSCM Memory Map/Register Definition....................................................................................................................632
30.4.1 CPU Configuration Memory Map and Registers...........................................................................................632
30.4.2 MSCM Register Descriptions........................................................................................................................ 632
Chapter 31
Flash Memory Controller (FMC)
31.1 Chip-specific FMC information....................................................................................................................................659
31.1.1 FMC masters..................................................................................................................................................659
31.2 Introduction...................................................................................................................................................................660
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31.2.1 Overview........................................................................................................................................................660
31.2.2 Features.......................................................................................................................................................... 660
31.3 Modes of operation....................................................................................................................................................... 661
31.4 External signal description............................................................................................................................................661
31.5 Functional description...................................................................................................................................................661
31.5.1 Default configuration..................................................................................................................................... 661
31.5.2 Speculative reads............................................................................................................................................662
31.6 Initialization and application information.....................................................................................................................663
Chapter 32
Flash Memory Module (FTFC)
32.1 Chip-specific FTFC information...................................................................................................................................665
32.1.1 Flash memory types....................................................................................................................................... 665
32.1.2 Flash memory sizes........................................................................................................................................666
32.1.3 Flash memory map.........................................................................................................................................666
32.1.4 Flash memory security...................................................................................................................................667
32.1.5 Power mode restrictions on flash memory programming..............................................................................667
32.1.6 Flash memory modes..................................................................................................................................... 667
32.1.7 Erase all contents of flash memory................................................................................................................667
32.1.8 Customize MCU operations via FTFC_FOPT register..................................................................................668
32.2 Introduction...................................................................................................................................................................668
32.2.1 Features.......................................................................................................................................................... 669
32.2.2 Block diagram................................................................................................................................................671
32.2.3 Glossary......................................................................................................................................................... 671
32.3 External signal description............................................................................................................................................674
32.4 Memory map and registers............................................................................................................................................674
32.4.1 Flash configuration field description............................................................................................................. 674
32.4.2 Program flash 0 IFR map...............................................................................................................................675
32.4.3 Data flash 0 IFR map..................................................................................................................................... 675
32.4.4 Register descriptions......................................................................................................................................678
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