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PCI Express Elastic Buffers
Introduction
Elastic Buffers (also known as Elasticity Buffers, Synchronization Buffers, and
Elastic Stores) are used to ensure data integrity when bridging two different clock
domains. This buffer is simply a FIFO (First-In-First-Out) where data is deposited
at a certain rate based on one clock and removed at a rate derived from a different
clock. Because these two clocks could (and almost always do) have minor
frequency differences, there is the potential for this FIFO to eventually overflow
or underflow. To avoid this situation, an Elastic Buffer has the ability to insert or
remove special symbols, during specified intervals that allow the buffer to
compensate for the clock differences.
The Elastic Buffer, or the concept of the Elastic Buffer, has been around since at
least 1960. Maurice Karnaugh was granted a patent for this technology back in
1963 for its use in transmitting Pulse-Code Modulated (PCM) signals in telephone
networks (Pat. 3,093,815). However, this was just the first of many applications
that these buffers would be used in. The robustness of Elastic Buffers is indicated
by their inclusion in modern day technologies. These buffers can be found in
protocols such as USB, InfiniBand, Fibre Channel, Gigabit Ethernet, and of
course PCI Express.
This paper describes the necessity of Elastic Buffers in a serialized, source-
synchronous timing architecture such as PCI Express. Next, a brief description of
the protocol used to implement clock tolerance compensation is discussed, as well
as the placement of the Elastic Buffer within the data flow of a PCI Express
device. Finally, this paper shows some viable implementations (including sizes)
of Elastic Buffers in PCI Express devices as well as the advantages and
disadvantages of each design.
The Need for Elastic Buffers
The PCI Express technology is a high-speed, serialized, source-synchronous
timing (clock-forwarding), data transfer protocol. These characteristics are
significantly different than the characteristics implemented by PCI Express’
predecessor buses, namely PCI and PCI-X. Both PCI and PCI-X use a multi-drop,
parallel bus that utilizes a synchronous timing architecture.
A synchronous timing architecture is where a common clock source supplies a
clock to all the devices on the bus, and that clock is used to enable the device’s
transceivers to clock data in and out. This scheme requires that the clocks arrive at
each device at precisely the same time. There is a very small amount of pin-to-pin
skew allowed, which means that the lengths of these clock traces have to be
4
弹性缓冲区(也称为弹性缓冲区、同步缓冲区和弹性存储)用于在桥接两个不同的时钟域时确保数据完整性。这个缓冲区就是一
个简单的FIFO(先进先出),其中数据以基于一个时钟的特定速率存储,并以来自另一个时钟的速率删除。因为这两个时钟可
能(而且几乎总是)有微小的频率差异,所以这个FIFO有可能最终溢出或下溢出。为了避免这种情况,弹性缓冲区能够在指定
的间隔内插入或删除特殊符号,从而允许缓冲区补偿时钟差异。
弹性缓冲,或弹性缓冲的概念,至少在1960年就出
现了。Maurice Karnaugh早在1963年就获得了这项
技术的专利,因为它用于在电话网络中传输脉冲码调
制(PCM)信号(Pat: 3,093,815)。然而,这只是将在许
多应用程序中使用这些缓冲区的第一个应用程序。弹
性缓冲器的坚固性由其在现代技术中的应用显示出
来。这些缓冲区可以在USB、InfiniBand、光纤通
道、千兆以太网,当然还有PCI Express等协议中找
到。
本文描述了在一个串行化的源中使用弹性缓冲器的必
要性
同步时序架构,如PCI Express。接下来,简要描述
用于实现时钟公差补偿的协议,以及在PCI
Express设备的数据流中放置弹性缓冲区。最后,本
文给出了弹性缓冲器在PCI Express设备中的一些可
行实现(包括尺寸)以及每种设计的优缺点。
弹性缓冲,或弹性缓冲的概念,至少在1960年就出现了。Maurice Karnaugh早在1963年就获得了这项技术的专利,因为它
用于在电话网络中传输脉冲码调制(PCM)信号(Pat: 3,093,815)。然而,这只是将在许多应用程序中使用这些缓冲区的第一个
应用程序。弹性缓冲器的坚固性由其在现代技术中的应用显示出来。这些缓冲区可以在USB、InfiniBand、光纤通道、千兆
以太网,当然还有PCI Express等协议中找到。
本文描述了在一个串行化的源中使用弹性缓冲器的必要性
同步时序架构,如PCI Express。接下来,简要描述用于实现时钟公差补偿的协议,以及在PCI Express设备的数据流中放置
弹性缓冲区。最后,本文给出了弹性缓冲器在PCI Express设备中的一些可行实现(包括尺寸)以及每种设计的优缺点。
PCI Express技术是一种高速的、串行的、源同步计时(时钟转发)的数据传输协议。这些特性
明显不同于PCI Express的前身总线(即PCI和PCI- x)实现的特性。PCI和PCI- x都使用使用同步
时序架构的多点滴并行总线。
同步计时体系结构是一个公共时钟源向总线上的所有设备提供一个时钟,该时钟用于使设备的收发器能
够输入和输出时钟数据。这个方案要求时钟精确地同时到达每个设备。有一个非常小的针对针偏差允
许,这意味着这些时钟轨迹的长度必须匹配,以最小化设备之间的偏差量。现在很明显,随着时钟速度
的增加,允许的针脚到针脚的偏差必须减少,这就要求匹配这些时钟轨迹的路由变得越来越困难。