Micron 2Gb NAND Flash Memory 技术规格

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" Micron 的 MT29F2G08ABAGAWP-IT 是一款基于 Open NAND Flash Interface (ONFI) 1.0 标准的 2Gb 单层单元（SLC）NAND 闪存内存。这款芯片提供高速的数据传输和高效的存储解决方案，适用于各种嵌入式和移动设备应用。" MT29F2G08ABAGAWP-IT 的主要特性包括： 1. **Open NAND Flash Interface (ONFI) 1.0 兼容性**：遵循 ONFI 1.0 规范，确保与其他支持该标准的控制器的兼容性，简化系统集成，提高数据传输效率。 2. **单层单元（SLC）技术**：采用 SLC 技术，SLC 提供更高的读写速度、更长的耐用性和更佳的能效，相较于多层单元（MLC）和三层单元（ TLC）NAND 闪存。 3. **内存组织结构**：页面大小为 2176 字节（2048 字节用户数据 + 128 字节 ECC），每页64个块（每个块128K+8K字节）。内存分为两个平面，每个平面有1024个块，总容量为2Gb（2048个块）。 4. **异步I/O性能**：tRC（读写循环时间）和 tWC（写完成时间）分别为20ns（3.3V）/ 30ns（1.8V）和同样数值，确保快速的数据存取。 5. **阵列性能**：读取页面速度为25微秒，编程页面速度为200微秒（典型值，3.3V/1.8V），擦除块时间为2毫秒（典型值）。 6. **高级命令集**：支持编程页面缓存模式、读取页面缓存模式、永久块锁定（块47:0）、一次性可编程（OTP）模式、块锁定、可编程驱动强度、双平面命令（仅在ECC关闭时可用）、读取唯一ID以及内部数据迁移功能。 7. **操作状态字节**：提供软件检测操作完成、成功/失败条件以及写保护状态的方法。 8. **Ready/Busy# (R/B#) 信号**：硬件方式检测操作完成，提供实时反馈。 9. **WP# 信号**：全设备写保护，确保数据安全。 10. **保留块**：块7-0被保留，可能用于特定用途或系统保留，不可由用户直接访问或编程。这款 NAND 闪存芯片广泛应用于需要高速读写、低功耗和高可靠性的产品中，如嵌入式系统、移动设备、SSD 存储等。其高性能、高稳定性和先进的特性使其成为对数据存储有严格要求的应用的理想选择。

Asynchronous Interface Bus Operation

The bus on the device is multiplexed. Data I/O, addresses, and commands all share the

same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and

commands are always supplied on I/O[7:0].

The command sequence typically consists of a COMMAND LATCH cycle, address input

cycles, and one or more data cycles, either READ or WRITE.

Table 3: Asynchronous Interface Mode Selection

Mode

CE# CLE ALE WE# RE# I/Ox WP#

Standby

H X X X X X 0V/V

Command input L H L H X H

Address input L L H H X H

Data input L L L H X H

Data output L L L H X X

Write protect X X X X X X L

Notes:

1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V

or V

2. WP# should be biased to CMOS LOW or HIGH for standby.

Asynchronous Enable/Standby

When the device is not performing an operation, the CE# pin is typically driven HIGH

and the device enters standby mode. The memory will enter standby if CE# goes HIGH

while data is being transferred and the device is not busy. This helps reduce power con-

sumption.

The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash devices on the

same bus.

A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Asynchronous Commands

An asynchronous command is written from I/O[7:0] to the command register on the ris-

ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.

Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some

commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are

accepted by die (LUNs) even when they are busy.

For devices with a x16 interface, I/O[15:8] must be written with zeros when a command

is issued.

Micron Confidential and Proprietary

2Gb: x8 NAND Flash Memory

Asynchronous Interface Bus Operation

CCMTD-1725822587-4081

m79a_2gb_ecc_off_embedded_nand.pdf – Rev. E 5/17 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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Micron 2Gb NAND Flash Memory 技术规格

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