TPD2S701-Q1汽车USB双通道保护芯片

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"TI-TPD2S701-Q1.pdf 是一款由Texas Instruments生产的汽车级USB双通道数据线保护器，适用于高速数据传输，如USB 2.0和USB 3.0接口。这款器件符合AEC-Q100标准，能在-40°C至125°C的温度范围内稳定工作，提供了VBUS短路保护以及IEC 61000-4-2和ISO 10605规定的±8kV和±15kV ESD保护。它还具有1GHz的高速数据开关能力，5V电源供电，可调节的过压保护阈值，快速的过压响应时间和热关断功能。此外，TPD2S701-Q1集成有输入使能和故障输出信号，确保数据完整性，并通过10引脚VSSOP或QFN封装实现小型化设计。此器件广泛应用在汽车终端设备，如音响主机、后座娱乐系统、远程信息处理、USB集线器、导航模块和媒体接口等。" TI的TPD2S701-Q1是专为汽车电子领域设计的一款高性能保护器件，其主要特点包括： 1. **符合AEC-Q100标准**：该器件满足汽车行业的可靠性要求，能够在恶劣的环境条件下稳定工作。 2. **VBUS短路保护**：在VD+和VD-之间提供VBUS短路保护，以防止电源线的异常情况对设备造成损害。 3. **ESD保护**：提供±8kV接触放电和±15kV气隙放电的ESD保护，符合IEC61000-4-2和ISO10605标准，有效保护USB接口免受静电冲击。 4. **高速数据开关**：具备1GHz的带宽，确保了USB 2.0和USB 3.0等高速数据接口的高效传输。 5. **5V电源供电**：仅需5V电源，简化了系统设计。 6. **可调节的OVP阈值**：用户可以根据具体需求调整过压保护的阈值。 7. **快速过压响应时间**：200ns的典型响应时间，能迅速应对过压事件，减少潜在的系统损坏。 8. **热关断特性**：当器件过热时，会自动关闭，以防止进一步损伤。 9. **输入使能和故障输出信号**：集成的控制逻辑使得管理和监控更加方便，故障输出可以及时反馈异常状态。 10. **封装选项**：10引脚VSSOP和10引脚QFN封装，小体积设计适应紧凑的汽车电子系统布局。 TPD2S701-Q1的应用场景广泛，涵盖了各种车载信息娱乐系统和接口，如车载音响、后座娱乐系统、远程信息处理单元、USB集线器、导航设备以及媒体接口等。这些应用都需要可靠的数据传输和保护，以保证车辆电子系统的稳定性和安全性。

TPD2S701-Q1

www.ti.com.cn

ZHCSGF6A –APRIL 2017–REVISED JULY 2017

Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VD_LEAK_3.6V

Leakage current on VD±

during normal operation

VD± Standard mode 0 or mode 1. Set VD± = 3.6 V.

D± = floating. Measure current flowing into VD±

2.5 4

µA

OVP_3.3V

Input overvoltage threshold

for VREF = 3.3 V

VD± Standard mode 1. R

TOP

= 140 kΩ ± 1%, R

BOT

24.9 kΩ ± 1%. Connect D± to 40-Ω load.

Measure the value at which FLTZ is asserted

3.61 4.14 4.67

OVP_0.66V

Input overvoltage threshold

for VREF = 0.66 V

VD± Standard mode 1. R

TOP

= 47.5 kΩ ± 1%, R

BOT

150 kΩ ± 1%. Connect D± to 40-Ω load.

Measure the value at which FLTZ is asserted

0.72 0.83 0.94

DATA LINE SWITCHES – VD+ to D+ or VD– to D–

On resistance

Mode 0 or 1. Set V

PWR

= 5 V; V

REF

= 3.3 V; EN

= 0 V; Measure resistance between D+ and

VD+ or D– and VD–, voltage between 0 and 0.4

4 6.5 Ω

ON(Flat)

On resistance flatness

Mode 0 or 1. Set V

PWR

= 5 V; V

REF

= 3.3 V; EN

= 0 V; Measure resistance between D+ and

VD+ or D– and VD–, sweep voltage between 0

and 0.4 V. Take difference of resistance at 0.4-

V and 0-V VD± bias

1 Ω

On bandwidth (–3-dB)

Mode 0 or 1. Set V

PWR

= 5 V; V

REF

= 3.3 V; EN

= 0 V; Measure S21 bandwidth from D+ to VD+

or D– to VD– with voltage swing = 400 mVpp,

Vcm = 0.2 V

960 MHz

6.8 Power Supply and Supply Current Consumption Chracteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UVLO_RISING_

VPWR

PWR

rising UVLO threshold

Use standard mode 0 set-up. Set EN = 0 V, load D+ to 45

Ω, VD+ = 3.3 V. Set V

PWR

= 3.5 V, and step up V

PWR

until

90% of VD+ appears on D+

3.7 3.95 4.2 V

UVLO_HYST_V

PWR

VPWR UVLO hysteresis

Use standard mode 0 set up. Set EN = 0 V, load D+ to 45

Ω, VD+ = 3.3 V. Set V

PWR

= 4.3 V, and step down

PWR

until D+ falls to 10% of VD+. This gives

UVLO_FALLING_VPWR

. V

UVLO_RISING_VPWR

–

UVLO_FALLING_VPWR

= V

UVLO_HYST_VPWR

for this unit

250 300 400 mV

UVLO_RISING_

VREF

VREF rising UVLO threshold

in mode 0

Use standard mode 0 set up. Set EN = 0V, load D+ to 45

Ω, VD+ = 3.3 V. Set VREF = 2.5 V, and step up

VREF until 90% of VD+ appears on D+

2.6 2.7 2.9 V

UVLO_HYST_V

REF

VREF UVLO hysteresis

Use standard mode 0 set up. Set EN = 0 V, load D+ to 45

Ω, VD+ = 3.3 V. Set VREF = 3 V, and step down

VREF until D+ falls to 10% of VD+. This gives

UVLO_FALLING_VREF

. V

UVLO_RISING_VREF

–V

UVLO_FALLING_VREF

= V

UVLO_HYST_VREF

for this unit

75 125 200 mV

VPWR_DISABLE

D_MODE0

PWR

disabled current

consumption

Use standard mode 0. EN = 5 V . Measure current into

PWR

110 µA

VPWR_DISABLE

D_MODE1

PWR

disabled current

consumption

Use standard mode 1. EN = 5 V. Measure current into

PWR

110 µA

VREF_DISABLE

VREF disabled current

consumption mode 0

Use standard mode 0. EN = 5 V. Measure current into

VREF

10 µA

VPWR_MODE0

PWR

pperating current

consumption

Use standard mode 0. EN = 0 V. Measure current into

PWR

250 µA

VPWR_MODE1

PWR

operating current

consumption

Use standard mode 1. EN = 0 V. Measure current into

PWR

350 µA

VREF

VREF operating current

consumption mode 0

Use standard mode 0. EN = 0 V. Measure current into

REF

12 20 µA

CHG_VREF

VREF fast charge current

Standard mode 1. 0.1 µF < C

VREF

< 3 µF. Set-up for

charging to 3.3 V. Use a high voltage capacitor that does

not derate capacitance up the 3.3 V. Measure slope to

calculate the current when C

VREF

cap is being

charged. Test to check this OPEN LOOP method

22 mA

TPD2S701-Q1

ZHCSGF6A –APRIL 2017–REVISED JULY 2017

www.ti.com.cn

Power Supply and Supply Current Consumption Chracteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

D_OFF_LEAK_S

Mode 0. Measured flowing into D+ or D– supply, V

PWR

= 0

V, VD+ or VD– = 18 V, EN = 0 V, V

REF

= 0 V, D± = 0 V

–1 1 µA

D_ON_LEAK_ST

Mode 0. Measured flowing into D+ or D– supply, V

PWR

= 5

V, VD+ or VD– = 18 V, EN = 0 V, V

REF

= 3.3 V, D± = 0 V

–1 1

µA

VD_OFF_LEAK_

STB

Mode 0. Measured flowing out of VD+ or VD– supply,

PWR

= 0 V, VD+ or VD– = 18 V, EN = 0 V, V

REF

= 0 V,

D± = 0 V

120

VD_ON_LEAK_S

Mode 0. Measured flowing out of VD+ or VD– supply,

PWR

= 5 V, VD+ or VD– = 18 V, EN = 0 V, V

REF

= 3.3 V,

D± = 0 V

120 µA

VPWR_TO_VRE

F_LEAK

Leakage from VPWR to

VREF

Use standard mode 0. Set VREF = 0 V. Measured

current flowing out of VREF pin

1 µA

VREF_TO_VPW

R_LEAK

Leakage from VREF to

VPWR

Use standard mode 0. Set VPWR = 0 V. Measured as

current flowing out of VPWR pin

1 µA

6.9 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

ENABLE PIN AND VREF FAST CHARGE

VREF_CHG

VREF fast charge time

Time between when 5 V is applied to V

PWR

, and V

REF

reaches V

VREF_FAST_CHG

. Needs to happen before or at

same time t

ON_STARTUP

completes

0.5 1 ms

ON_STARTU

P_MODE0

Device turnon time from UVLO

mode 0

Mode 0. EN = 0 V, measured from V

PWR

and V

REF

UVLO

to data FET ON, V

PWR

comes to UVLO

second.

Place 3.3 V on VD±. Ramp VREF to 3.3 V, then VPWR

to 5 V and measure the time it takes for D± to reach 90%

of VD±

0.5 1 ms

ON_STARTU

P_MODE1

Device turnon time from UVLO

mode 1

Informative. mode 1. EN = 0 V, measured from V

PWR

UVLO

to data FET ON

0.5 +

CHG_C

VREF

ON_STARTU

P_MODE1_3.3V

Device turnon time from UVLO

mode 1

Mode 1. EN = 0 V, measured from V

PWR

= UVLO

data FET ON, C

VREF

= 1 µF, V

REF_FINAL

= 3.3 V.

Measure the time it takes for D± to reach 90% of VD±

0.6 1 ms

ON_EN_MOD

Device turnon time mode 0

Mode 0. V

PWR

= 5 V, V

REF

= 3.3 V, time from EN is

asserted until data FET is ON. Place 3.3 V on VD±,

measure the time it takes for D± to reach 90% of VD±

150 µs

ON_EN_MOD

Device turnon time mode 1

Mode 1. V

PWR

= 5 V, V

REF_INITIAL

= 0 V, time from EN is

asserted until data FET is ON. Place 3.3 V on VD±,

measure the time it takes for D± to reach 90% of VD±

150 +

CHG_V

REF

µs

ON_EN_MOD

E1_3.3V

Device turnon time mode 1 for

VREF = 3.3 V

Mode 1. V

PWR

= 5 V, V

REF_INITIAL

= 0 V, time from EN is

asserted until data FET is ON. Place 3.3 V on VD±,

measure the time it takes for D± to reach 90% of

VD±. C

VREF

= 1 µF, VREF_FINAL = 3.3 V

300 µs

OFF_EN

Device turnoff time

Mode 0 or 1. V

PWR

= 5 V, V

REF

= 3.3 V, time from EN is

deasserted until data FET is off. Place 3.3 V on VD±,

measure the time it takes for D± to fall to 10% of

VD±, R

D±

= 45 Ω

5 µs

CHG_CVREF

Time to charge C

VREF

Informative. Mode 1. Time from V

REF

= 0 V to 80% ×

REF_FINAL

after EN transitions from high to low

VREF

× 0.8

REF_FI

NAL

)/(I

HG_VREF

)

CHG_CVREF

_3.3V

Time to charge C

VREF

to 3.3 V

Mode 1. Time from V

REF

= 0 V to 90% × 3.3 V after EN

transitions from high to low, C

VREF

= 1 µF

132 µs

剩余35页未读，继续阅读

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TPD2S701-Q1汽车USB双通道保护芯片

TI-TPD2S703-Q1.pdf

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