AFE539A4：集成式智能模拟前端，适用于多种控制应用

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"TI-AFE539A4是一款由德州仪器(TI)推出的智能模拟前端(AFE)芯片，主要用于各种应用，包括激光控制、化学和气体分析、机器人感应等。该芯片集成了四通道10位DAC和ADC，以及比例积分(PI)控制器功能，支持I2C和SPI接口，具备广泛的电压和电流输出能力，同时提供了灵活的配置选项，如可编程增益、比较器模式和输出钳位。AFE539A4能在电源关闭时保持高阻抗输出，并有自动检测I2C或SPI接口的能力。此外，它还支持内部、外部或VDD基准源，并能在宽电源电压和温度范围内工作。封装形式为16引脚WQFN，尺寸为3mm x 3mm。" TI的AFE539A4是一款高度集成的模拟前端解决方案，其主要特点和功能如下： 1. **集成式比例积分(PI)控制**：该芯片内置PI控制器，允许10位ADC输入和10位DAC输出。它可以从非易失性存储器(NVM)独立运行，具有可编程的比例和积分增益，以适应不同应用的需求。 2. **电压和电流输出**：AFE539A4提供10位电压输出，具有低INL和DNL，支持1x到4x的不同增益设置。同时，它还提供8位电流输出，输出范围包括±25μA、±50μA、±125μA和±250μA。 3. **比较器功能**：所有通道都可以配置为ADC、DAC或比较器，且比较器输入适合输出钳位，输出端有可编程的最小值、最大值和共模值。 4. **灵活性与配置**：AFE539A4允许用户通过MODE引脚在编程模式和独立模式之间切换，所有通道都可编程为ADC或DAC，比较器模式也可自定义。 5. **电源管理与保护**：该芯片在VDD关闭时提供高阻抗输出，以保护系统。另外，它支持自动检测I2C或SPI接口，且GPIO引脚可用于多功能用途。 6. **用户可编程NVM**：通过NVM，用户可以存储和调用自定义设置，实现特定应用的定制化。 7. **工作条件**：AFE539A4的工作电源电压范围为1.8V至5.5V，工作温度范围覆盖-40°C至+125°C，使其适用于各种恶劣环境。 8. **封装与尺寸**：采用16引脚WQFN封装，尺寸仅为3mm x 3mm，满足小型化需求。在热电制冷(TEC)控制应用中，AFE539A4因其集成的PI控制器和灵活的输出选项，能够有效控制TEC模块的温度，确保系统的稳定性和效率。此外，由于其智能特性，AFE539A4在无微处理器的系统中也能发挥重要作用，简化了设计流程并提高了系统的可重复使用性。

6.10 Timing Requirements: I

C Standard Mode

all input signals are timed from VIL to 70% of V

, 1.8 V ≤ V

≤ 5.5 V, –40°C ≤ T

≤ +125°C, and 1.8 V ≤ V

pull-up

≤ V

MIN NOM MAX UNIT

SCLK

SCL frequency 100 kHz

BUF

Bus free time between stop and start conditions 4.7 µs

HDSTA

Hold time after repeated start 4 µs

SUSTA

Repeated start setup time 4.7 µs

SUSTO

Stop condition setup time 4 µs

HDDAT

Data hold time 0 ns

SUDAT

Data setup time 250 ns

LOW

SCL clock low period 4700 ns

HIGH

SCL clock high period 4000 ns

Clock and data fall time 300 ns

Clock and data rise time 1000 ns

6.11 Timing Requirements: I

C Fast Mode

all input signals are timed from VIL to 70% of V

, 1.8 V ≤ V

≤ 5.5 V, –40°C ≤ T

≤ +125°C, and 1.8 V ≤ V

pull-up

≤ V

MIN NOM MAX UNIT

SCLK

SCL frequency 400 kHz

BUF

Bus free time between stop and start conditions 1.3 µs

HDSTA

Hold time after repeated start 0.6 µs

SUSTA

Repeated start setup time 0.6 µs

SUSTO

Stop condition setup time 0.6 µs

HDDAT

Data hold time 0 ns

SUDAT

Data setup time 100 ns

LOW

SCL clock low period 1300 ns

HIGH

SCL clock high period 600 ns

Clock and data fall time 300 ns

Clock and data rise time 300 ns

6.12 Timing Requirements: I

C Fast Mode Plus

all input signals are timed from VIL to 70% of V

, 1.8 V ≤ V

≤ 5.5 V, –40°C ≤ T

≤ +125°C, and 1.8 V ≤ V

pull-up

≤ V

MIN NOM MAX UNIT

SCLK

SCL frequency 1 MHz

BUF

Bus free time between stop and start conditions 0.5 µs

HDSTA

Hold time after repeated start 0.26 µs

SUSTA

Repeated start setup time 0.26 µs

SUSTO

Stop condition setup time 0.26 µs

HDDAT

Data hold time 0 ns

SUDAT

Data setup time 50 ns

LOW

SCL clock low period 0.5 µs

HIGH

SCL clock high period 0.26 µs

Clock and data fall time 120 ns

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AFE539A4

ZHCSNR0 – AUGUST 2021

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6.12 Timing Requirements: I

C Fast Mode Plus (continued)

all input signals are timed from VIL to 70% of V

, 1.8 V ≤ V

≤ 5.5 V, –40°C ≤ T

≤ +125°C, and 1.8 V ≤ V

pull-up

≤ V

MIN NOM MAX UNIT

Clock and data rise time 120 ns

6.13 Timing Requirements: SPI Write Operation

all input signals are timed from VIL to 70% of V

, V

= 1.8 V to 5.5 V, and –40°C ≤ T

≤ +125°C

MIN NOM MAX UNIT

(SCLK)

Serial clock frequency, 1.7 V ≤ V

≤ 5.5 V

25 MHz

SCLKHIGH

SCLK high time, 1.7 V ≤ V

≤ 5.5 V

18 ns

SCLKLOW

SCLK low time, 1.7 V ≤ V

≤ 5.5 V

18 ns

SDIS

SDI setup time, 1.7 V ≤ V

≤ 5.5 V

8 ns

SDIH

SDI hold time, 1.7 V ≤ V

≤ 5.5 V

8 ns

CSS

CS to SCLK falling edge setup time, 1.7 V ≤ V

≤ 5.5 V

18 ns

CSH

SCLK falling edge to CS rising edge, 1.7 V ≤ V

≤ 5.5 V

10 ns

CSHIGH

CS hight time, 1.7 V ≤ V

≤ 5.5 V

50 ns

DACWAIT

Sequential DAC update wait time for same channel, 1.7 V ≤ V

≤ 5.5 V

2 µs

BCASTWAIT

Broadcast DAC update wait time, 1.7 V ≤ V

≤ 5.5 V

2 µs

6.14 Timing Requirements: SPI Read and Daisy Chain Operation

all input signals are timed from VIL to 70% of V

, V

= 1.8 V to 5.5 V, and –40°C ≤ T

≤ +125°C

MIN NOM MAX UNIT

(SCLK)

Serial clock frequency, 1.7 V ≤ V

≤ 5.5 V

1 MHz

SCLKHIGH

SCLK high time, 1.7 V ≤ V

≤ 5.5 V

400 ns

SCLKLOW

SCLK low time, 1.7 V ≤ V

≤ 5.5 V

400 ns

SDIS

SDI setup time, 1.7 V ≤ V

≤ 5.5 V

8 ns

SDIH

SDI hold time, 1.7 V ≤ V

≤ 5.5 V

8 ns

CSS

CS to SCLK falling edge setup time, 1.7 V ≤ V

≤ 5.5 V

400 ns

CSH

SCLK falling edge to CS rising edge, 1.7 V ≤ V

≤ 5.5 V

10 ns

CSHIGH

CS hight time, 1.7 V ≤ V

≤ 5.5 V

1 µs

6.15 Timing Requirements: GPIO

all input signals are timed from VIL to 70% of V

, V

= 1.8 V to 5.5 V, and –40°C ≤ T

≤ +125°C

MIN NOM MAX UNIT

GPIHIGH

GPI high time, 1.7 V ≤ V

≤ 5.5 V

(1)

2 µs

GPILOW

GPI low time, 1.7 V ≤ V

≤ 5.5 V

(1)

2 µs

GPAWGD

LDAC falling edge to DAC update delay, 1.7 V ≤ V

≤ 5.5 V

(2)

2 µs

CS2LDAC

CS rising edge to LDAC falling edge, 1.7 V ≤ V

≤ 5.5 V

1 µs

STP2LDAC

C stop bit rising edge to LDAC falling edge, 1.7 V ≤ V

≤ 5.5 V

1 µs

LDACW

LDAC low time, 1.7 V ≤ V

≤ 5.5 V

2 µs

(1) The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations.

(2) The GPIOs can be configured as channel-specific or global LDAC function. In a channel-specific LDAC mode, the LDAC pins can be

used to trigger DAC code patterns stored in the NVM.

AFE539A4

ZHCSNR0 – AUGUST 2021

www.ti.com.cn

ADVANCE INFORMATION

12 Submit Document Feedback

Product Folder Links: AFE539A4

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