信号完整性和电源完整性联合设计：I/O接口的功率完整性

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"《Power Integrity for I/O Interfaces: With SI/PI Co-Design》是由Vishram S. Pandit、Woong Hwan Ryu和Myoung Joon Choi合著的一本专业书籍，由Prentice Hall出版社在2010年出版。这本书深入探讨了信号完整性和电源完整性在接口设计中的联合应用，对于学习和实践SI（信号完整性）/PI（电源完整性）具有极大的价值。全书共有8章，内容包括输入输出接口、电磁效应、电源/地线和信号分布网络、频域分析、时域分析、信号完整性与电源完整性相互作用、以及联合分析和测量方法。" 本书的核心知识点如下： 1. 输入输出接口（Input Output Interface）：这部分主要讨论了系统中的数据传输通道，包括其设计原则、标准协议（如USB、PCIe等）以及接口类型，如单端驱动器和接收器、差分驱动器和接收器等。 2. 电磁效应（Electromagnetic Effects）：电磁效应是影响信号完整性和电源完整性的关键因素。书中详细阐述了这些效应如何影响信号传输的质量，以及它们如何在信号和电源之间产生耦合噪声，进而影响系统的性能。 3. 电源/地线和信号分布网络（Power/Ground and Signal Distribution Network）：这部分讲解了电源和地线网络的设计原则，强调了它们对信号完整性的影响。良好的电源和地线布局能有效降低噪声，提高系统的稳定性。 4. 频域分析（Frequency Domain Analysis）：通过傅里叶变换等工具进行频域分析，可以识别信号在不同频率下的特性，找出可能的干扰源，从而优化设计。 5. 时域分析（Time Domain Analysis）：时域分析关注信号的瞬态响应，如上升时间、下降时间和抖动等，这对于高速数字系统来说至关重要，因为这些参数直接影响数据传输的准确性和可靠性。 6. 信号完整性与电源完整性相互作用（Signal Integrity/Power Integrity Interaction）：这两者的交互可能导致系统性能下降，如信号失真、噪声增加等。理解这种互动关系有助于找出问题的根源并提出解决方案。 7. 信号完整性/电源完整性联合分析（Signal Integrity/ Power Integrity Co-Analysis）：书中介绍了如何同时考虑信号完整性和电源完整性，实现协同设计，以提高整体设计的效率和质量。 8. 测量方法（Measurements）：最后，书中还涵盖了实际工程中进行SI/PI测量的技巧和方法，包括如何选择合适的测试设备、解读测量结果等。《Power Integrity for I/O Interfaces: With SI/PI Co-Design》是一本深入研究信号完整性和电源完整性的权威教材，适合电子工程师、设计师以及对高速数字系统感兴趣的读者阅读，可以帮助他们理解和解决实际工作中遇到的信号和电源完整性问题。

Myoung Joon Choi is a technical lead in the Signal/Power Integrity

Engineering team at Intel Corporation. He works on developing

methodologies for high-speed interface simulation and analysis. His focus

areas include high-speed system SI-PI co-simulation, on-chip signal and

power integrity, and computational analysis of entire high-speed systems.

Dr. Choi has received a Ph.D. and an M.S. from University of Illinois at

Urbana-Champaign, Urbana, IL, USA, and a BS from Korea University,

Seoul, Korea. He has authored and co-authored many technical publications

in journals and conferences.

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Massachusetts laws.

Chapter 1. Introduction

In a digital electronic system, when high-speed signals pass through the

interconnect network, different unwanted effects such as Inter Symbol

Interference (ISI) and crosstalk are produced that degrade the signal

integrity. Power integrity is related to noise in the Power Distribution

Network (PDN). Various techniques have been developed to model and

design the PDN and analyze the noise impact [1, 2]. Simultaneously

Switching Output (SSO) noise is produced when charging/discharging

currents from the multiple buffers go through the PDN. This noise affects

the circuit response and produces timing skews and delays. The power

noise is coupled to signals at the chip level and at the interconnect level. It

is becoming increasingly essential to determine not only the PDN noise, but

also the margin degradation due to the noise coupling to signals. Due to

ISI, crosstalk, SSO, and combinations thereof, the signal quality and timing

margin becomes degraded at the receiver. System designers need to

consider a concurrent design methodology to evaluate power integrity and

its effects on signal integrity.

1.1. Digital Electronic System

The digital electronic system comprises a processing unit and an I/O

controller unit. Different types of data flow from one part of the system to

others in digital format, on different buses. Internal buses communicate

within the different components of the system, and external buses

communicate with the external devices. Various networking devices

communicate with the digital electronic system with different protocols and

standards. The I/O controller unit manages various types of input and

output data on the buses and networking devices. The processing unit and

the I/O controller unit are on different integrated circuits or chips in a

conventional personal computer system, whereas they are on the same chip

in a System-on-chip– (SoC) based platform. The I/O controller unit has

several I/O interfaces that communicate with different I/Os. Figure 1.1

shows the block diagram of a typical I/O interface in a digital system.

Figure 1.1. Input output interface

A single-ended driver has one output port and assumes a common ground

or power connection as a reference. For a single-ended receiver, there is

one input port that assumes a common ground or power connection as a

reference. In this chapter and in Chapter 2, “I/O Interfaces,” generic

nomenclature is used for power (Power) and ground (Gnd) nodes, for the

driver as well as the receiver. Power nodes are electrically different from the

driver and the receiver due to PDN parasitics. Similarly, the ground nodes

are electrically different for the driver and the receiver.

The single-ended signaling scheme with two input terminals at the receiver

is shown in Figure 1.3. Similar to the previous scheme, it also has a single

output terminal at the driver. This terminal is referenced to common power

or ground.

Figure 1.3. Single-ended link with Vref at RX

However, at the receiver end, there is one input terminal along with a

locally generated reference voltage (Vref). This receiver has a differential

amplifier, so it is similar to a pseudo differential receiver. Overall link is still

a single-ended link. This locally generated Vref is on the Printed Circuit

Board (PCB) and is primarily used to compensate the DC and low-frequency

voltage drop. A single-ended push-pull driver can be designed in a current

mode or a voltage mode configuration [4].

A single-ended signal has a power or ground reference or both. The

referencing scheme can be identified by the proximity of the signal line to

the power or ground domains. The proximity of the signal to the power or

ground domain tends to make a return path to the domain in high

frequencies, because capacitive coupling makes a low impedance path

between the signal and that domain. Frequently, unintentional referencing

change occurs in complex multilayer PCBs. When the si

nal is routed on the

board from one layer to the other layer, there may be some regions with

signal over void. The signal’s reference change due to the vertical structure

inside of a rather flat power/ground domain structure works as one of the

major sources of unintended radial wave propagation. It contributes to

signal noise and power delivery noise when it is captured by other

structures inside of the PCB. In addition to referencing change, rather loose

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