Xilinx数字预失真（DPD）IP Core产品指南

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Xilinx DPDP（数字预失真）文档 Xilinx DPDP（数字预失真）文档是一份非常有价值的资料，适合学习和使用预失真技术的人员收藏。下面是从这份文档中提取的相关知识点：一、概述数字预失真（Digital Pre-Distortion，DPD）是一种技术，用于改善无线通信系统中的线性度。Xilinx DPDP是基于FPGA的数字预失真解决方案，旨在提高无线通信系统的性能和可靠性。二、产品规格 Xilinx DPDP的产品规格包括： * 标准：符合业界标准，例如3GPP和LTE * RF性能：高频率和高带宽的RF性能 * IP定时性能：高速的IP处理能力 * 资源利用率：高效的资源利用率 * 数据路径延迟：低延迟的数据处理 * 端口描述：灵活的端口配置 * 寄存器空间：大容量的寄存器空间三、设计指南在设计Xilinx DPDP时，需要考虑以下几点： * 时钟设计：选择合适的时钟频率和时钟域 * 复位设计：正确的复位和时钟sequencing * 协议描述：正确的协议描述和实现 * 核心生成：正确的核心生成和配置四、设计流程 Xilinx DPDP的设计流程包括： * 核心自定义和生成 * 用户参数配置 * 输出生成 * 约束核心 * 模拟和实现五、测试和应用 Xilinx DPDP的测试和应用包括： * 测试台架构 * 应用软件开发 * Zynq-7000单处理器裸机配置 * Zynq-7000双处理器AMP配置 * Zynq-7000双处理器Linux SMP配置 * Zynq UltraScale+ MPSoC单处理器裸机配置六、结论 Xilinx DPDP是一份非常有价值的资料，涵盖了数字预失真技术的各个方面。通过学习和应用Xilinx DPDP，可以提高无线通信系统的性能和可靠性。

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PG076 July 3, 2017

Chapter 3

Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the

core.

Clocking

This core requires five clock input signals.

dpd_aclk

Signal dpd_aclk is used to drive the main data interface logic within the design. Its clock

frequency determines the data rate of the DPD IP core. All AXI4-Stream interfaces

(s_axis_din, m_axis_dout, s_axis_srx, m_axis_srx_ctrl) are synchronous to this

clock.

dpd_internal_aclk

Signal dpd_internal_aclk is used to clock the internal datapath logic. When using the

two-phase hybrid configuration, this clock should be phase-aligned but double the

frequency of dpd_aclk; for the single and non-hybrid two-phase configurations, this clock

should be tied to the same source clock as dpd_aclk.

s_axi_user_aclk

Signal s_axi_user_aclk is a dedicated input for the AXI4-Lite interface that provides

asynchronous access to the shared memory for passing instructions to, and reading status

from the DPD IP software application running on the ARM® processor.

s_axi_ctrl_aclk

This s_axi_ctrl_aclk clock is used to time all transfers on the s_axi_ctrl interface.

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Chapter 3: Designing with the Core

s_axi_ctrl_2x_aclk

The s_axi_ctrl_2x_aclk is used to over-clock internal logic. This clock has a strict

requirement that it is phase aligned and double the frequency of s_axi_ctrl_aclk.

Hardware acceleration performance is closely tied to this clock.

RECOMMENDED: Xilinx recommends that the maximum achievable frequency is applied to

s_axi_ctrl_2x_aclk with s_axi_ctrl_aclk being set to exactly half that frequency.

Resets

All reset signals have active-Low sensitivity.

In the design, dpd_aresetn is the main reset and should be synchronous to dpd_aclk;

this is used to reset all system logic and the software state in the design. Asserting

dpd_aresetn immediately disables the output data and initiates a software controlled

reset process that reinitializes the system to a power-on state including clearing any

parameters provided on the host interface. After deasserting dpd_aresetn, you must wait

for the DPD to indicate that it is ready through the host interface and then reapply any

configuration parameters specific to your system.

The AXI4-Lite user interface has its own dedicated reset, s_axi_user_aresetn, and

must be synchronous to s_axi_user_aclk. It resets all AXI4-Lite interface logic and will

prevent any communication on the user interface. Hence, it must only be applied when no

transactions are pending on the user interface.

The reset s_axi_ctrl_aresetn is specific to the interface used by the DPD software

application to communicate with the hardware.

Reset and Clock Sequencing

The standard power-on sequencing of reset and clocks is as follows:

1. Power-On: assert dpd_aresetn, s_axi_ctrl_aresetn, s_axi_user_aresetn

2. Bring-Up Bus Clocks: bring-up s_axi_ctrl_acllk, s_axi_ctrl_2x_aclk,

s_axi_user_aclk. Once these clocks are stable, de-assert s_axi_ctrl_aresetn

and s_axi_user_aresetn.

3. Start DPD Software: Once it is possible to communicate on s_axi_ctrl interface, then

the DPD Software can start running. However, it will wait for de-assertion of

dpd_aresetn.

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Chapter 3: Designing with the Core

4. Bring Up Data Rate Clocks: Once dpd_aclk and dpd_2x_aclk are stable, then

dpd_aresetn can be de-asserted.

5. Follow the Instructions in DPD Application Software Boot Process section of Chapter 6,

Application Software to start the DPD process.

To power-down or reset the system, the above steps must be reversed. When DPD

Application is running, dpd_aresetn can be applied at anytime whilst the system is

operating. It will disable the output and will initiate a reset process within the DPD

Software. Operation of DPD can be re-started, starting from step 4.

To power-down the system further, the operation of the DPD Software must be terminated.

To end operation of the DPD, the KILL_DPD control mode must be issued. See Software

Control Modes for more information. Access on the s_axi_user interface should also be

stopped. At this point, it is possible to apply the bus interface resets

s_axi_ctrl_aresetn and s_axi_user_aresetn.

Protocol Description

The DPD IP core requires various interfaces to the DFE system for successful operation of

the design. The DPD v8.0 core uses AXI4 interfaces for both data and control. The presence

of AXI4, AXI4-Lite and AXI4-Stream interfaces brings standardization and enhanced

interoperability of Xilinx® IP LogiCORE™ solutions. For further details on AXI4 interfaces

see the AMBA AXI4-Stream Protocol Specification (IHI 0051A) [Ref 3], Xilinx AXI Design

Reference Guide (UG1037) [Ref 4] and ARM AMBA AXI and ACE Protocol Specification (IHI

0022D) [Ref 5].

Datapath AXI4-Stream Interfaces

The input TX (baseband) data is received through the slave interface (s_axis_din) and

outputs pre-distorted data through the master interface (m_axis_dout) with the width of

the tdata streams sized according to the number of antennas and phases.

The basic element of the datapath is a 32-bit complex sample composed of 16 bits of real

and imaginary signed data concatenated with the real component in the lower 16 bits of the

32-bit word. The total width of the datapath is then determined by the number of transmit

antennas and the number of phases. For one phase, the input data for each antenna should

be concatenated as per Table 3-1.

Table 3-1: One Phase Per Antenna Concatenation

Antenna 1 Antenna 0

QI QI

63:48 47:32 31:16 15:0

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Chapter 3: Designing with the Core

For two-phase data, the two complex samples per clock per antenna are concatenated as

shown in Table 3-2 where sample S0 precedes sample S1 in the serial data stream.

For data widths other than 16 bits, pad or round the data as appropriate to form the input

data for a particular transmit path based on an understanding of the signal statistics and

dynamics. Where the bit width is less than 16 bits it should be zero-padded at the LSB, and

where it is greater than 16 bits it should be symmetrically rounded; in both cases, it is

important to ensure that the sign bit is retained. The data out contains a corresponding 32

bits for each transmit path which can be connected to a digital mixer or complex

digital-to-analog converter (DAC). If the TX DAC has a lower bitwidth (14 bits, for example),

symmetric rounding should be applied to convert the signals from 16 to 14 bits. Symmetric

rounding is required to prevent any unwanted DC offset, which introduces a spur in the

transmitted spectrum in cases where the signal itself has no DC energy, for example

wideband code division multiple access (WCDMA) carrier configurations [0 0 1] and [1 0 1].

After power-up or reset, the core is idle until s_axis_din_tvalid has been asserted for

the first time; s_axis_din_tready is held High and m_axis_dout_tvalid is held Low

by the core until this occurs. After this, the core is synchronized and expects data input and

provides data output every clock cycle. After synchronization, the core expects

s_axis_din_tvalid to remain asserted, otherwise an underrun condition occurs. As the

core is free-running, underrun causes the preceding data sample to be input for a second

time internally. Underrun is signaled by asserting the event_s_din_underrun flag for a

single clock cycle after the condition has occurred.

The s_axis_din_tuser field is used to supply sideband/control information alongside

the tdata field in real time. It contains one byte per antenna, with byte 0 being used by

antenna 0, byte 1 by antenna 1 and so on. Information on s_axis_din_tuser is output

on m_axis_dout_tuser and is delayed to match the latency of the DPD Filter. The use of

bits within each byte of TUSER and the field packing for each antenna byte is shown in

Table 3-3.

Table 3-2: Two Phases Per Antenna Concatenation

Antenna 1 Antenna 0

S1 S0 S1 S0

QIQIQIQI

127:112 111:96 95:80 79:64 63:48 47:32 31:16 15:0

Table 3-3: TUSER Field Packing for each Byte

Bits Name Description

7:4 user bits

Available for customer use.

Demo System uses bit 4 to carry Power Amplifier Enable

Signal in TDD system.

3 capture sync Used as capture reference point by DPD

alternate frame

marker

Alternative Frame Marker. For example, GSM Framing in

Multi-RAT System

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PG076 July 3, 2017

Chapter 3: Designing with the Core

The frame and slot marker are not used but might be required for future feature

enhancements. The capture synchronization strobe is used with capture mode 1 (See

Updating and Reporting DPD Parameters). The capture is triggered CAPTUREDELAY

samples after a rising-edge is detected on the capture synchronization bit (Capture Sync)

which is internally sampled by dpd_aclk. You can assert this bit for one or more cycles of

dpd_aclk; the capture is triggered relative to when it was asserted and it is irrelevant how

many cycles it is asserted for.

After the core has received its first valid data on the s_axis_din interface,

m_axis_dout_tvalid is asserted a number of cycles later equal to the core latency; after

this, it remains permanently asserted to indicate valid output samples on the

m_axis_dout_tdata port every cycle. The core expects the data to be read by asserting

m_axis_dout_tready every cycle while the data updates with a new output sample. If an

output sample is not read each cycle due to m_axis_dout_tready being deasserted,

then the overrun condition occurs. As the core is free-running, overrun causes the next

output sample to be dropped internally, as the current one has not been read and remains

on the output port m_axis_dout_tdata. Overrun is signaled by asserting the

event_m_dout_overrun flag for a single cycle.

Figure 3-1 shows an example timing diagram. The timing diagram shows the first slave valid

pulse which synchronizes the interfaces and initiates the free running flow of data into and

out of the core. The diagrams demonstrate invalid operation as signaled by the underrun

and overrun flags.

1 frame marker

Primary framing signal. Typically 10ms time-base in 3G/4G

Systems.

0 slot marker Indicates Data Slot. Also used by Xilinx PC-CFR IP Core.

X-Ref Target - Figure 3-1

Figure 3-1: AXI4-Stream Datapath Interface

Table 3-3: TUSER Field Packing (Cont’d)for each Byte

Bits Name Description

dpd_aclk

dpd_aresetn

s_axis_din_tdata

s_axis_din_tvalid

s_axis_din_tready

event_s_din_underrun

m_axis_dout_tdata

m_axis_dout_tvalid

m_axis_dout_tready

event_m_dout_overrun

DIN

DOUT

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