现代内存层次结构的实用数据压缩技术

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"Practical Data Compression for Modern Memory Hierarchies" 是一份由Gennady G. Pekhimenko于2016年7月在卡内基梅隆大学完成的博士学位论文，CMU-CS-16-116。这份论文主要探讨了针对现代内存层次结构的实用数据压缩技术。在现代计算机系统中，内存层次结构是关键性能优化的领域，它包括从高速缓存到主内存再到硬盘等不同级别的存储。论文作者在指导委员会 Todd C. Mowry、Onur Mutlu 等专家的指导下，深入研究了如何通过数据压缩提高这些层次结构的效率。论文的内容可能涉及以下几个方面： 1. 数据压缩的基本原理：可能介绍了各种数据压缩算法，如霍夫曼编码、LZ77、LZ78、Burrows-Wheeler变换等，以及它们如何减少数据的存储需求。 2. 内存层次结构的理解：详细分析了现代计算机系统的内存层次，包括CPU缓存、主内存和外部存储之间的交互，以及它们对系统性能的影响。 3. 压缩与性能：研究数据压缩如何在不显著增加计算开销的情况下提升内存访问速度，降低存储带宽需求，并减少能源消耗。 4. 实验与评估：可能包含了实际实验来对比不同压缩技术在各种内存层次中的效果，以及如何优化这些技术以适应不同的应用场景。 5. 应用场景：讨论了数据压缩在数据库管理、大数据处理、云计算和嵌入式系统等领域的应用可能性和挑战。 6. 行业支持：论文的研究得到了国家科学基金会、国防高级研究计划局、半导体研究公司等多个机构的资助，以及AMD、Google等公司的支持，反映了该领域的重要性和实际需求。 7. 未来方向：可能提出了未来研究的潜在方向，如进一步提高压缩效率，或者将压缩技术与其他优化策略（如缓存替换策略）结合。这份论文为理解和优化现代计算机系统的内存层次结构提供了新的视角，通过数据压缩技术，为提升系统性能和能效提供了一种实用的方法。

6.3 Normalized bit toggle count vs. compression ratio (with the FPC algo-

rithm) for each of the discrete GPU applications. . . . . . . . . . . . . . 121

6.4 Bit toggles without compression. . . . . . . . . . . . . . . . . . . . . . . 122

6.5 Bit toggles after compression. . . . . . . . . . . . . . . . . . . . . . . . 122

6.6 Energy Control decision mechanism. . . . . . . . . . . . . . . . . . . . . 124

6.7 Bit toggle count w/o and with Metadata Consolidation. . . . . . . . . . . 125

6.8 System overview with interconnect compression and EC. . . . . . . . . . 126

6.9 System overview with off-chip bus compression and EC. . . . . . . . . . 126

6.10 Effect of Energy Control on the number of toggles on DRAM bus. . . . . 130

6.11 Effective DRAM bandwidth increase for different applications. . . . . . . 131

6.12 Effect of Energy Control with C-Pack compression algorithm on the num-

ber of DRAM toggles. . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

6.13 Effective DRAM bandwidth increase with C-Pack algorithm. . . . . . . . 132

6.14 Speedup with C-Pack compression algorithm. . . . . . . . . . . . . . . . 134

6.15 Effect on the DRAM energy with C-Pack compression algorithm. . . . . 135

6.16 Effect of Energy Control on the number of toggles in on-chip interconnect. 136

6.17 Effect of Energy Control on compression ratio in on-chip interconnect. . . 136

6.18 Effect of Energy Control on performance when compression is applied to

on-chip interconnect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.19 Effect of Energy Control on on-chip interconnect energy. . . . . . . . . . 139

6.20 Effect of Metadata Consolidation on DRAM bit toggle count with FPC

compression algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

7.1 Performance comparison (IPC) of different compressed designs. . . . . . 145

7.2 Effect of cache and main memory compression on memory bandwidth. . . 146

7.3 Effect of cache and main memory compression on DRAM bus energy. . . 147

xvi

Core

On‐Chip

Caches

Main

Memory

NoC Channel

CPU,GPU SRAM DRAM,PCM

Application

Compiler

Figure 1.1: Data compression from the core to the main memory.

rithm that is suitable for on-chip cache compression. This algorithm solves one of the

key challenges for cache compression: achieving low decompression latency, which is on

the critical path of the execution. Then, we show that compressed cache block size is a

new important factor when making cache replacement decisions that helps to outperform

state-of-the-art cache replacement mechanisms.

We then propose a new design for main memory compression that solves a key chal-

lenge in realizing data compression in main memory: the disparity between how the data is

stored (i.e., at a page granularity) and how it is accessed (i.e., at a cache line granularity).

Finally, we show that bandwidth compression—both on-chip and off-chip—can be ef-

ﬁcient in providing high effective bandwidth in the context of modern GPUs (with more

than a hundred real applications evaluated). At the same time, we ﬁnd that there is a new

important problem with bandwidth compression that makes it potentially energy inefﬁcient

– the signiﬁcant increase in the number of bit toggles (i.e., the number of transitions be-

tween zeros and ones) that leads to an increase in dynamic energy. We provide an efﬁcient

solution to this problem.

1.1.1 A Compelling Possibility: Compressing Data throughout the

Full Memory Hierarchy

At ﬁrst glance, data compression may seem like an obvious approach to reducing the neg-

ative impacts of processing large amounts of data. In theory, if data compression could

effectively reduce the size of the data without introducing signiﬁcant overheads, it would

relieve pressure on both the capacity of the various layers of the memory hierarchy (in-

cluding caches, DRAM, non-volatile memory technologies, etc.) as well as the bandwidth

of the communication channels (including memory buses, etc.) that transfer data between

these layers. This in turn would allow system designers to avoid over-provisioning these

resources, since they could deliver performance more efﬁciently as a function of system

cost and/or power budget. Perhaps surprisingly, although forms of data compression have

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现代内存层次结构的实用数据压缩技术

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