Hyperstone E1-32XSR/E1-16XSR：32位RISC/DSP微处理器技术规格

32XSR

16XSR

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"E1-32XSR/E1-16XSR 数据手册提供了关于hyperstone E1-32XSR和E1-16XSR微处理器的详细信息，这些处理器是E1-32X和E1-16X的进一步发展。通过采用先进的0.25微米CMOS工艺，处理器的最大时钟速率得到了提升。由于与前代产品引脚兼容，它们可以直接替换现有设计中的处理器，前提是考虑到了变化的电压供应要求。用户手册包含了处理器的规格、信息以及可能的变化，但不构成Hyperstone AG的承诺。" **E1-32XSR和E1-16XSR处理器详解** E1-32XSR和E1-16XSR是32位RISC/DSP微处理器，是Hyperstone公司产品线的一部分。这两款处理器基于0.25微米CMOS工艺，显著提高了其运行速度，为高性能计算应用提供了更强的处理能力。引脚兼容性使得设计者能够在不改变硬件设计的情况下，轻松升级到新型号的处理器，这在系统升级和维护中具有很高的价值。 **技术规格与特性** - **时钟速率提升**: 通过更先进的制造工艺，E1-32XSR和E1-16XSR的最高工作频率得到提升，从而提高了处理速度和效率。 - **RISC/DSP架构**: 结合了RISC（精简指令集计算机）的高效能和DSP（数字信号处理）的处理能力，使其适合于需要高效计算和信号处理的领域，如通信、音频和视频处理等。 - **引脚兼容性**: 与前一代产品E1-32X和E1-16X保持引脚兼容，简化了升级流程，但用户需要注意新的电压供应要求，以确保处理器正常运行。 - **变更与改进**: Hyperstone AG保留对产品进行改进的权利，用户手册中列出的规格可能会有变化，用户应时刻关注最新的更新。 **安全性和责任声明** Hyperstone AG明确指出，其微处理器不应用于生命支持系统，因为处理器故障可能直接威胁生命或造成伤害。如果用户选择在生命支持应用中使用Hyperstone微处理器，所有风险由用户自行承担，并同意赔偿Hyperstone AG因此产生的任何损失。 **版权和许可** 该手册的所有内容受版权保护，未经Hyperstone AG的明确许可，不得以任何形式复制或传播，包括电子和机械方式，如影印和录音。 **联系信息** 对于更多关于E1-32XSR和E1-16XSR处理器的信息，用户可以直接联系Hyperstone AG获取详细支持和服务。 E1-32XSR和E1-16XSR是高性能、可升级的微处理器，适用于需要强大处理能力和高效率的系统设计。然而，它们的应用需谨慎，特别是在生命支持等关键领域。用户必须遵守Hyperstone AG提供的所有指导，确保正确和安全的使用。

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Page 1-8 Architecture

1.3. Global Register Set

The architecture provides 32 global registers of 32 bits each. These are:

G0 Program Counter PC

G1 Status Register SR

G2 Floating-Point Exception Register FER

G3..G15 General purpose registers

G16..G17 Reserved

G18 Stack Pointer SP

G19 Upper Stack Bound UB

G20 Bus Control Register BCR (see section 6. Bus Interface)

G21 Timer Prescaler Register TPR (see section 5. Timer)

G22 Timer Compare Register TCR (see section 5. Timer and CPU Clock

Modes)

G23 Timer Register TR (see section 5. Timer and CPU Clock Modes)

G24 Watchdog Compare Register WCR (see section 6. Bus Interface)

G25 Input Status Register ISR (see section 6. Bus Interface)

G26 Function Control Register FCR (see section 6. Bus Interface)

G27 Memory Control Register MCR (see section 6. Bus Interface)

G28..G31 Reserved

Registers G0..G15 can be addressed directly by the register code (0..15) of an instruction.

Registers G18..G27 can be addressed only by a MOV or MOVI instruction with the high

global flag H set to 1.

E1-32XSR User’s Manual Page 1-11

The status register SR contains the following status information:

C Bit zero is the carry condition flag C. In general, when set it indicates that the

unsigned integer range has been exceeded. At add operations, it indicates a

carry out of bit 31 of the result. At subtract operations, it indicates a borrow

(inverse carry) into bit 31 of the result.

Z Bit one is the zero condition flag Z. When set, it indicates that all 32 or 64

result bits are equal to zero regardless of any carry, borrow or overflow.

N Bit two is the negative condition flag N. On compare instructions, it indicates

the arithmetic correct (true) sign of the result regardless of an overflow. On all

other instructions, it is derived from result bit 31, which is the true sign bit

when no overflow occurs. In the case of overflow, result bit 31 and N reflect

the inversion of the true sign.

V Bit three is the overflow condition flag V. In general, when set it indicates a

signed overflow.

M Bit four is the cache-mode flag M. Besides being set or cleared under program

control, it is also automatically cleared by a Frame instruction and by any

branch taken except a delayed branch. See section 1.9. Instruction Cache for

details.

H Bit five is the high global flag H. When H is set, denotation of G0..G15 addres-

ses G16..G31 instead. Thus, the registers G18..G27 may be addressed by deno-

ting G2..G11 respectively.

The H flag is effective only in the first cycle of the next instruction after it was

set; then it is cleared automatically.

Only the MOV or MOVI instruction issued as the next instructions can be used

to copy the content of a local register or an immediate value to one of the high

global registers. The MOV instruction can also be used to copy the content of a

high global register (except the BCR, TPR, FCR and MCR register, which are

write-only) to a local register. With all other instructions, the result may be

invalid.

If one of the high global registers is addressed as the destination register in user

state (S = 0), the condition flags are undefined, the destination register remains

unchanged and a trap to Privilege Error occurs.

Reserved Bit six is reserved for future use. It must always be zero.

I Bit seven is the interrupt-mode flag I. It is set automatically on interrupt entry

and reset to its old value by a Return instruction. The I flag is used by the

operating system; it must be never changed by any user program, regardless of

user or supervisor state.

FTE Bits 12..8 are the floating-point trap enable flags (see section 3.33.2. Floating-

Point Instructions).

FRM Bits 14..13 are the floating-point rounding modes (see section 3.33.2. Floating-

Point Instructions).

Page 1-12 Architecture

L Bit 15 is the interrupt-lock flag L. When the L flag is one, all Interrupt, Parity

Error and Extended Overflow exceptions regardless of individual mode bits are

inhibited. The state of the L flag is effective immediately after any instruction

which changed it. The L flag is set to one by any exception.

The L flag can be cleared or kept set in any or on return to any privilege state

(user or supervisor). Changing the L flag from zero to one is privileged to

supervisor or return from supervisor to supervisor state. A trap to Privilege

Error occurs if the L flag is set under program control from zero to one in user

or on return to user state.

The following status information cannot be changed by addressing the SR:

T Bit 16 is the trace-mode flag T. When both the T flag and the trace pending

flag P are one, a trace exception occurs after every instruction except after a

Delayed Branch instruction. The T flag is cleared by any exception.

Note: The T flag can only be changed in the saved return SR and is then

effective after execution of a Return instruction.

P Bit 17 is the trace pending flag P. It is automatically set to one by all in-

structions except by the Return instruction, which restores the P flag from bit

17 of the saved return SR.

Since for a Trace exception both the P and the T flag must be one, the P flag

determines whether a trace exception occurs (P = 1) or does not occur (P = 0)

immediately after a Return instruction which restored the T flag to one.

Note: The P flag can only be changed in the saved SR. No program except the

trace exception handler should affect the saved P flag. The trace exception

handler must clear the saved P flag to prevent a trace exception on return, in

order to avoid tracing the same instruction in an endless loop.

S Bit 18 is the supervisor state flag S (see section 1.5. Privilege States). It is set

to one by any exception.

ILC Bits 20 and 19 represent the instruction-length code ILC. It is updated by

instruction execution. The ILC holds (in general) the length of the last in-

struction: ILC values of one, two or three represent an instruction length of

one, two or three half-words respectively. After a branch taken, the ILC is

invalid. The Return instruction clears the ILC.

Note: Since a Return instruction following an exception clears the ILC, a

program must not rely on the current value of the ILC.

FL Bits 24..21 represent the frame length FL. The FL holds the number of usable

local registers (maximum 16) assigned to the current stack frame.

FL = 0 is always interpreted as FL = 16.

FP Bits 31..25 represent the frame pointer FP. The least significant six bits of the

FP point to the beginning of the current stack frame in the local register set,

that is, they point to L0.

The FP contains bit 8..2 of the address at which the content of L0 would be

stored if pushed onto the memory part of the stack.

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Hyperstone E1-32XSR/E1-16XSR：32位RISC/DSP微处理器技术规格

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XSR/SIP SERDES

CEI 56G XSR中的XSR是什么意思

15:43:43,418 DEBUG com.xzsoft.frame.updateEbs.mapper.UpdateEbsMapper.updateZjptEbsZhbm:142 - ==> Preparing: {call xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm(?, ?,?, ?,?)} 15:43:43,419 DEBUG com.xzsoft.frame.updateEbs.mapper.UpdateEbsMapper.updateZjptEbsZhbm:142 - ==> Parameters: null, null, null

<![CDATA[ {call xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm(to_date(#{p_upt_date,jdbcType=VARCHAR},'yyyy-MM-dd'), #{p_svr_id = 1,jdbcType=DECIMAL},#{p_db_lnk = xzfs,jdbcType=VARCHAR}, #{flag,mode=OUT,jdbcType=DECIMAL},#{msg,mode=OUT,jdbcType=VARCHAR})} ]]>

<![CDATA[ {call xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm(p_upt_date = to_date(#{p_upt_date,jdbcType=VARCHAR},'yyyy-MM-dd'), p_svr_id = 1,p_db_lnk = xzfs, #{flag,mode=OUT,jdbcType=DECIMAL},#{msg,mode=OUT,jdbcType=VARCHAR})} ]]>

<![CDATA[ {call xsr_xz_ba_ebs_d_pkg.down_gl_flex(#{flag,mode=OUT,jdbcType=DECIMAL},#{msg,mode=OUT,jdbcType=VARCHAR})} ]]>

"select c.ou_bank_id ,\n" + " c.bank_alias ,\n" + " c.bank_name ,\n" + " c.bank_acc_name ,\n" + " c.bank_acc_no \n" + " from xsr_xz_ba_ou_bank c\n" + " where c.ou_id = '"+me.DEF_OU_ID+"'\n" + " and c.bank_alias like '%##P%'";

<![CDATA[ {call xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm(#{p_svr_id = 1,jdbcType=DECIMAL},#{p_db_lnk = xzfs,jdbcType=VARCHAR}, #{flag,mode=OUT,jdbcType=DECIMAL},#{msg,mode=OUT,jdbcType=VARCHAR})} ]]>

调用存储过程函数，存储过程为xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm，参数为p_svr_id，p_upt_date，p_db_lnk，其中p_svr_id，p_db_lnk两个参数用map赋给固定值

<![CDATA[ {call xsr_xz_ba_ebs_d_pkg.down_mtl_zhbm(#{p_svr_id,mode=IN,jdbcType=VARCHAR}, #{p_upt_date,mode=IN,jdbcType=TIMESTAMP},#{p_db_lnk,mode=IN,jdbcType=VARCHAR}, #{flag,mode=OUT,jdbcType=DECIMAL},#{msg,mode=OUT,jdbcType=VARCHAR})} ]]>

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