Marvell 88E6095芯片技术规格与应用
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收藏 3.16MB PDF 举报 "88E6095是Marvell公司的一款网络交换芯片，适用于构建具有服务质量（QoS）和802.1Q VLAN支持的网络解决方案。该芯片集成了100M交换接口，同时提供了3个千兆以太网（GE）端口，以实现高效能的网络连接。其设计目标是实现低功耗和低成本，特别适合对能耗和成本敏感的网络设备应用。芯片还具备MII（Media Independent Interface）接口，允许与各种类型的物理层（PHY）器件进行通信。
88E6095的主要特性包括：
1. **高性能**: 提供8个快速以太网（FE）端口和3个千兆以太网端口，支持线速交换，确保数据传输的高速稳定。
2. **QoS支持**: 通过精细的流量管理和优先级调度，保证关键业务的服务质量，例如视频流、VoIP等实时应用。
3. **802.1Q VLAN功能**: 支持虚拟局域网，能够灵活地管理和隔离网络流量，提高网络安全性。
4. **低功耗设计**: 优化的电源管理策略降低了芯片的运行功耗，有利于节能和降低散热需求。
5. **MII接口**: 提供了与PHY芯片的兼容性，使得系统设计更加灵活。
6. **堆叠能力**: 可以通过特定技术将多个88E6095芯片堆叠起来，扩展端口数量和增强网络容量。
7. **安全特性**: 集成了一些安全功能，如端口保护、风暴控制，有助于防止网络攻击和异常流量。
8. **软件兼容性**: 通常会提供相应的驱动程序和开发工具，以便于系统集成和应用程序开发。
然而，值得注意的是，Marvell不对其产品在生命维持设备或可能导致生命威胁情况的应用中的使用提供任何保证。因此，88E6095不适合用于医疗等高风险领域。
文档MV-S102629-00 Rev.C是关于88E6092/88E6095/88E6095F的数据手册，包含了详细的芯片规格、电气特性、引脚配置以及应用示例，为设计者提供了全面的技术参考。尽管Marvell保留随时更新此文档的权利，但文档中提供的所有信息可能不完全准确或完整，用户在实际应用中应结合最新的芯片规格和应用指南。"
Doc. No. MV-S102629-00 Rev. C
CONFIDENTIAL
Copyright © 2006 Marvell
Page 16 Document Classification: Proprietary Information June 9, 2006, Advance
Link Street
®
88E6092/88E6095/88E6095F
8 FE + 3 GE Stackable Ethernet Switch with QoS and 802.1Q
List of Figures
Figure 1: 88E6092/88E6095 Device 176 TQFP EPAD Package Pinout............................................................ 18
Figure 2: 88E6095F Device 216 LQFP EPAD Package Pinout ......................................................................... 19
Figure 3: 16 FE + 2 GE Ports............................................................................................................................. 56
Figure 4: 24 FE + 2 GE with 88E6095 X 3......................................................................................................... 57
Figure 5: 48 FE + 4 GE wit 88E6095 X 6 + 88E6185 ........................................................................................ 58
Figure 6: Fiber to the Curb................................................................................................................................. 59
Figure 7: SOHO/SMB Router with FE and GE Ports ......................................................................................... 59
Figure 8: MII MAC Interface Pins ....................................................................................................................... 64
Figure 9: MII PHY Interface Pins........................................................................................................................ 65
Figure 10: GMII MAC Interface Pins .................................................................................................................... 66
Figure 11: GMII PHY Interface Pins..................................................................................................................... 67
Figure 12: Switch Data Flow ................................................................................................................................ 69
Figure 13: Format of an ATU Entry ...................................................................................................................... 86
Figure 14: Switch Operation with VLANs Disabled .............................................................................................. 94
Figure 15: Switch Operation with a Typical Router VLAN Configuration .............................................................95
Figure 16: Switch Operation with another Example VLAN Configuration ............................................................ 96
Figure 17: Format of a VTU Entry...................................................................................................................... 100
Figure 18: IEEE Tag Frame Format................................................................................................................... 105
Figure 19: IPv4 Priority Frame Format............................................................................................................... 108
Figure 20: IPv6 Priority Frame Format............................................................................................................... 108
Figure 21: IPv4 IGMP Snoop Format................................................................................................................. 109
Figure 22: IPv6 MLD Snoop Format .................................................................................................................. 110
Figure 23: Ingress Forward Tag Format ............................................................................................................ 112
Figure 24: Ingress From_CPU Tag Format........................................................................................................ 113
Figure 25: Ingress Header Format ..................................................................................................................... 116
Figure 26: Double Tag Format........................................................................................................................... 117
Figure 27: Switch Queues.................................................................................................................................. 120
Figure 28: IEEE Tag Frame Format................................................................................................................... 124
Figure 29: Double Tag Format........................................................................................................................... 125
Figure 30: Egress Forward Tag Format ............................................................................................................. 128
Figure 31: Egress To_CPU Tag Format ........................................................................................................... 129
Figure 32: Egress Header Format...................................................................................................................... 131
Figure 33: Device Transmit Block Diagram........................................................................................................ 136
Figure 34: Device Receive Block Diagram......................................................................................................... 137
Figure 35: Line Loopback Data Path.................................................................................................................. 151
Figure 36: Possible Solutions for Case One ...................................................................................................... 155
Figure 37: Possible Solutions for Case Two ...................................................................................................... 156
Figure 38: Serial LEDENA High Clocking with COLX in Dual Mode, Error Off, and DUPLEX in Single Mode.. 157
Figure 39: Serial LED Conversion...................................................................................................................... 158
Figure 40: Typical MDC/MDIO Read Operation................................................................................................. 162
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