Features
T7 Datasheet(Revision 1.1) Copyright© 2018 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 18
2.11. Security Engine
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Encryption and decryption algorithms implemented by using hardware, including AES,DES and 3DES
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Signature and verification algorithms implemented by using hardware, including RSA512,RSA1024,RSA2048
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HASH tamper proofing algorithms implemented by using hardware, including SHA1,SHA256,SHA384,SHA512,
HMAC_SHA1 and HMAC_SHA256
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True hardware random number(TRNG) generator and pseudo hardware random number(PRNG) generator
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Integrated 2.5 Kbits efuse storage space
2.12. External Peripherals
2.12.1. USB
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One USB 2.0 OTG(USB0), with integrated USB 2.0 analog PHY
- Compatible with USB2.0 Specification
- Supports High-Speed (HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s) and Low-Speed(LS,1.5 Mbit/s) in host mode
- Supports High-Speed (HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s) in device mode
- Complies with Enhanced Host Controller Interface(EHCI)Specification, Version 1.0, and the Open Host Controller
Interface(OHCI) Specification, Version 1.0a for host mode
- Up to 10 User-Configurable Endpoints for Bulk, Isochronous and Interrupt bi-directional transfers (Endpoint1,
Endpoint2, Endpoint3, Endpoint4, Endpoint5)
- Supports (8KB+64Bytes) FIFO for EPs(including EP0)
- Supports point-to-point and point-to-multipoint transfer in both host and peripheral mode
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Three USB 2.0 Host(USB1,USB2,USB3), with integrated USB 2.0 analog PHY
- Compatible with Enhanced Host Controller Interface(EHCI)Specification, Version 1.0, and the Open Host
Controller Interface (OHCI) Specification, Version 1.0a.
- Supports High-Speed (HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s) and Low-Speed(LS,1.5 Mbit/s) device
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One USB HSIC, share USB3 controller with one USB 2.0 analog PHY
2.12.2. EMAC
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Compliant with IEEE 802.3-2002 standard
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Supports 10/100/1000 Mbit/s data transfer rates
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Supports MII/RMII/RGMII PHY interface
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Supports both full-duplex and half-duplex operation
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Supports MDIO
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Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 Kbytes
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Supports a variety of flexible address filtering modes
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Separate 32-bit status returned for transmission and reception packets
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Optimization for packet-oriented DMA transfers with frame delimiters
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Supports linked-list descriptor list structure
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Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each descriptor can
transfer up to 4 Kbytes of data
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Comprehensive status reporting for normal operation and transfers with errors
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4 Kbytes TXFIFO for transmission packets and 16 Kbytes RXFIFO for reception packets
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Programmable interrupt options for different operational conditions
2.12.3. TWI
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Up to 10 TWIs(7 in CPU domain, 3 in CPUS domain)
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Software-programmable for Slave or Master
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Supports Repeated START signal