STM32G030F6P6 Cortex-M0+微控制器数据手册

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"STM32G030F6P6是STMicroelectronics公司生产的一款基于Arm Cortex-M0+内核的32位微控制器，适用于嵌入式硬件系统，特别是单片机应用。该芯片拥有最高64KB的闪存和8KB带硬件奇偶校验检查的SRAM，支持多种通信接口、定时器、ADC等功能，工作电压范围在2.0V至3.6V之间，具备低功耗模式，并且有多种时钟管理选项。" STM32G030F6P6的数据手册详细介绍了这款微控制器的主要特性，包括： 1. **核心处理器**：采用Arm Cortex-M0+处理器，运行频率高达64MHz，这使得它在低功耗应用中能提供高性能的计算能力。 2. **工作温度范围**：能够在-40°C至85°C的环境中稳定工作，适应各种气候和工业环境。 3. **内存配置**：提供最大64KB的闪存，用于存储程序代码和固件；8KB的SRAM，其中包含硬件奇偶校验功能，增强了数据安全性。 4. **CRC计算单元**：内置CRC计算模块，可用于数据校验，确保数据传输的完整性。 5. **电源管理和复位**：支持2.0V至3.6V的电压范围，具备电源上电/掉电复位（POR/PDR）功能。此外，还包括睡眠、停止和待机等低功耗模式，以及VBAT供电，用于RTC和备份寄存器在主电源断开时保持工作。 6. **时钟管理**：具有4至48MHz的晶体振荡器，32kHz晶体振荡器带校准，一个16MHz的内部RC振荡器可选配PLL，以及一个32kHz的内部RC振荡器，精度为±5%。 7. **I/O端口**：最多44个快速I/O，所有I/O都可以映射到外部中断向量，部分I/O支持5V耐压，增强了接口兼容性。 8. **DMA控制器**：5通道DMA控制器允许高效的数据传输，且能灵活映射。 9. **模拟转换器**：集成12位ADC，转换时间仅为0.4µs，可扩展连接最多16个外部通道。通过硬件过采样可提升至16位精度，转换范围0至3.6V。 10. **定时器功能**：包含16位高级电机控制定时器和四个16位通用定时器，满足不同类型的定时和计数需求。这些特性使STM32G030F6P6成为适用于多种应用的微控制器，如物联网设备、电机控制、传感器接口、智能家居产品以及各种工业控制应用。开发人员可以根据其丰富的外设和灵活的性能配置来设计高效的嵌入式系统。

Functional overview STM32G030x6/x8

16/94 DS12991 Rev 4

3.7.4 Low-power modes

By default, the microcontroller is in Run mode after system or power reset. It is up to the

user to select one of the low-power modes described below:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Low-power run mode

This mode is achieved with V

CORE

supplied by the low-power regulator to minimize the

regulator's operating current. The code can be executed from SRAM or from Flash,

and the CPU frequency is limited to 2 MHz. The peripherals with independent clock can

be clocked by HSI16.

• Low-power sleep mode

This mode is entered from the low-power run mode. Only the CPU clock is stopped.

When wakeup is triggered by an event or an interrupt, the system reverts to the Low-

power run mode.

• Stop 0 and Stop 1 modes

In Stop 0 and Stop 1 modes, the device achieves the lowest power consumption while

retaining the SRAM and register contents. All clocks in the V

CORE

domain are stopped.

The PLL, as well as the HSI16 RC oscillator and the HSE crystal oscillator are

disabled. The LSE or LSI keep running. The RTC can remain active (Stop mode with

RTC, Stop mode without RTC).

Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode,

so as to get clock for processing the wakeup event. The main regulator remains active

in Stop 0 mode while it is turned off in Stop 1 mode.

• Standby mode

The Standby mode is used to achieve the lowest power consumption, with POR/PDR

always active in this mode. The main regulator is switched off to power down V

CORE

domain. The low-power regulator is switched off. The PLL, as well as the HSI16 RC

oscillator and the HSE crystal oscillator are also powered down. The RTC can remain

active (Standby mode with RTC, Standby mode without RTC).

For each I/O, the software can determine whether a pull-up, a pull-down or no resistor

shall be applied to that I/O during Standby mode.

Upon entering Standby mode, register contents are lost except for registers in the RTC

domain and standby circuitry.

The device exits Standby mode upon external reset event (NRST pin), IWDG reset

event, wakeup event (WKUP pin, configurable rising or falling edge) or RTC event

(alarm, periodic wakeup, timestamp, tamper), or when a failure is detected on LSE

(CSS on LSE).

3.7.5 Reset mode

During and upon exiting reset, the schmitt triggers of I/Os are disabled so as to reduce

power consumption. In addition, when the reset source is internal, the built-in pull-up

resistor on NRST pin is deactivated.

Functional overview STM32G030x6/x8

18/94 DS12991 Rev 4

3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and

the peripherals. It also manages clock gating for low-power modes and ensures clock

robustness. It features:

• Clock prescaler: to get the best trade-off between speed and current consumption,

the clock frequency to the CPU and peripherals can be adjusted by a programmable

prescaler

• Safe clock switching: clock sources can be changed safely on the fly in run mode

through a configuration register.

• Clock management: to reduce power consumption, the clock controller can stop the

clock to the core, individual peripherals or memory.

• System clock source: three different sources can deliver SYSCLK system clock:

– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE). It

can supply clock to system PLL. The HSE can also be configured in bypass mode

for an external clock.

– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software. It can

supply clock to system PLL.

– System PLL with maximum output frequency of 64 MHz. It can be fed with HSE or

HSI16 clocks.

• Auxiliary clock source: two ultra-low-power clock sources for the real-time clock

(RTC):

– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting four drive

capability modes. The LSE can also be configured in bypass mode for using an

external clock.

– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to

clock an independent watchdog.

• Peripheral clock sources: several peripherals ( I2S, USARTs, I2Cs, ADC) have their

own clock independent of the system clock.

• Clock security system (CSS): in the event of HSE clock failure, the system clock is

automatically switched to HSI16 and, if enabled, a software interrupt is generated. LSE

CPU (hard fault) TIM1,16,17 Timer break Y - -

GPIO

TIMx External trigger Y Y -

ADC Conversion external trigger Y Y -

Table 4. Interconnect of peripherals (continued)

Interconnect source

Interconnect

destination

Interconnect action

Run

Low-power run

Sleep

Low-power sleep

Stop

DS12991 Rev 4 19/94

STM32G030x6/x8 Functional overview

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

• Clock output:

– MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

– LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 5 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

• Single-AHB master

• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

• Access, as source and destination, to on-chip memory-mapped devices such as Flash

memory, SRAM, and AHB and APB peripherals

• All DMA channels independently configurable:

– Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

– Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

– Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

– Support of transfers from/to peripherals to/from memory with circular buffer

management

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