![](https://csdnimg.cn/release/download_crawler_static/12535215/bg14.jpg)
................................
23-15
Figure 23-4
Basic AES/CSA PID Structure....................................................................................................
23-15
Figure 24-1
UART Block Diagram....................................................................................................................
24-4
Figure 24-2
IrDA SIR RNDEC Block Diagram
.................................................................................................
24-7
Figure 24-3
Baud rate divisor
.........................................................................................................................
24-10
Figure 24-4
UART Character Frame..............................................................................................................
24-14
Figure 24-5
IrDA Data Modulation (3/16)
.......................................................................................................
24-14
Figure 24-6
DMA Transfer Waveforms
..........................................................................................................
24-17
Figure 24-7
Smart Card Adepter Interface.....................................................................................................
24-21
Figure 25-1
USB 2.0 OTG Block Diagram
.......................................................................................................
25-2
Figure 25-2
Charge Pump Connection
............................................................................................................
25-6
Figure 26-1
USB2.0 HOST Block Diagram
......................................................................................................
26-2
Figure 27-1
Block Diagram of the I2S Controller
.............................................................................................
27-2
Figure 27-2
Basic Clock Tree...........................................................................................................................
27-4
Figure 27-3
I2S Audio Serial Data Formats
.....................................................................................................
27-5
Figure 27-4
TX FIFO Structure for BLC =
00 or BLC = 01...............................................................................
27-8
Figure 27-5
TX FIFO Structure for BLC = 10 (24 bits/channel)
.......................................................................
27-9
Figure 27-6
RX FIFO Structure for BLC = 00 or BLC = 01
............................................................................
27-11
Figure 27-7
RX FIFO Structure for BLC = 10 (24 bits/channel)
.....................................................................
27-12
Figure 28-1
AC97 Block Diagram
....................................................................................................................
28-2
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Figure 21-5
Data Transfer on the I2C-Bus.......................................................................................................
21-6
Figure 21-6
Arbitration Procedure between Two Masters
...............................................................................
21-7
Figure 21-7
Clock Synchronization
..................................................................................................................
21-8
Figure 21-8
Acknowledge on the I2C-Bus
.......................................................................................................
21-9
Figure 21-9
Timing on the SCL and SDA.......................................................................................................
21-11
Figure 21-10
Functional Block Diagram of I2C-Bus.......................................................................................
21-12
Figure 21-11
Master Transmitter Mode Operation.........................................................................................
21-13
Figure 21-12
Master Receiver Mode Operation.............................................................................................
21-14
Figure 21-13
Slave Transmitter Mode Operation...........................................................................................
21-15
Figure 21-14
Slave Receiver Mode Operation...............................................................................................
21-16
Figure 21-15
Linked Layer of the I2C-Bus
.....................................................................................................
21-17
Figure 21-16
Delays between the I2C-Bus Commands.................................................................................
21-17
Figure 22-1
SPI/SSP Block Diagram
...............................................................................................................
22-2
Figure 22-2
Texas Instruments Synchronous Serial Frame Format (Single Transfer)
....................................
22-7
Figure 22-3
TI Synchronous Serial Frame Format (Continuous Transfer)
......................................................
22-8
Figure 22-4
Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0
...............................
22-10
Figure 22-5
Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0
.......................
22-10
Figure 22-6
Motorola SPI Frame Format with SPO = 0 and SPH = 1
...........................................................
22-12
Figure 22-7
Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0
...............................
22-13
Figure 22-8
Motorola SPI Frame Format (Continuous Transfer) with SPO = 1
and SPH = 0
.......................
22-13
Figure 22-9
Motorola SPI Frame Format with SPO = 1 and SPH = 1
...........................................................
22-15
Figure 22-10
Microwire frame format (single transfer)
...................................................................................
22-16
Figure 22-11
Microwire Frame Format (Continuous Transfers).....................................................................
22-17
Figure 22-12
Microwire Frame Format
3-2
Figure 23-2
MPEG TS Timing at Serial Mode..................................................................................................
23-2
Figure 23-3
Capture