恩智浦i.MX 6ULL应用处理器中文参考手册

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"i.MX 6ULL 应用处理器参考手册是针对NXP半导体公司推出的i.MX 6ULL处理器的一份详细技术文档。该手册由Google翻译为中文，便于中文用户理解。手册涵盖了处理器的架构、内存系统、中断处理、外设接口等多个方面的内容，是开发基于i.MX 6ULL平台的硬件和软件工程师的重要参考资料。" 在i.MX 6ULL应用处理器参考手册中，主要包含以下几个关键知识点： 1. **内存映射**：手册详细介绍了i.MX 6ULL的内存映射，包括内存系统的概述、ARM平台内存映射以及不同类型的内存如DDR、EIM(外部接口模块)的配置和访问方式。这有助于开发者理解和配置处理器的内存资源。 2. **处理器架构**：手册提供了一个简化的框图来展示处理器的架构，包括CPU核心（如Cortex-A7）、内存接口和外设。此外，还概述了架构分区，帮助读者理解处理器内部的不同组件及其功能。 3. **中断系统**：针对Cortex-A7内核的中断处理进行了详细描述，这对于编写实时操作系统或驱动程序的开发者尤为重要。 4. **DMA（直接存储器访问）**：手册讨论了DMA控制器的功能，包括其在数据传输中的作用，这对于高效地利用系统资源进行大量数据传输至关重要。 5. **EIM（外部接口模块）**：EIM用于连接外部存储器和闪存设备，手册提供了EIM的配置方案和功能介绍，帮助开发者正确设置和使用这些接口。 6. **启动熔丝和锁定熔丝**：手册包含了启动和锁定熔丝的图解，这些熔丝在设备初始化和安全特性设置中起到关键作用。 7. **调试系统组件**：手册涵盖了处理器的调试功能，包括ATB（AMBA跟踪总线）和调试系统的组件，为软件调试和问题排查提供了指南。 8. **多模式DDR控制器（MMDC）**：详细阐述了MMDC的概述和功能，对于管理高速DDR内存的配置和操作提供了指导。 9. **SDMA（简单直接内存访问）**：介绍了SDMA事件映射，这有助于理解如何利用SDMA引擎进行高效的内存操作。整体而言，这份i.MX 6ULL应用处理器参考手册是开发人员深入理解该处理器特性和功能的重要工具，无论是硬件设计还是固件开发，都能从中获得必要的信息和支持。

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16 恩智浦半导体

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算法说明.........................................................................................................................................513

16.7.2ASRC中断使能寄存器(ASRC_ASRIER).....................................................................................529

16.7.11ASRC通道计数器寄存器(ASRC_ASRCCR).....................................................................................544

16.7.20ASRC76kHz以ASRC处理时钟(ASRC_ASR76K)表示的周期...........................549

16.7.13对x的ASRC数据输出寄存器（ASRC_ASRDOn）...........................................................................545

信号处理流程...........................................................................................................⋯⋯⋯⋯513

16.7.4ASRC过滤器配置状态寄存器(ASRC_ASRCFG)..................................................................532

16.7.22A对的ASRC杂项控制寄存器（ASRC_ASRMCRA）...................................................................................551

16.5.1.2.1

16.7.6ASRC时钟分频器寄存器1(ASRC_ASRCDR1).....................................................................................537

16.7.15A对低部分的ASRC理想比率(ASRC_ASRIDRLA).....................................................................546

16.5.1.2

16.7.8ASRC状态寄存器（ASRC_ASRSTR）...........................................................................................................539

16.6启动程序......................................................................................................................................................................519

16.7.17ASRC对B低部分的理想比率(ASRC_ASRIDRLB)...................................................................................547

16.5.1

16.7.1ASRC控制寄存器(ASRC_ASRCTR)........................................................................................................526

16.7.10ASRCASRC任务队列FIFO寄存器1（ASRC_ASRTFR1）...........................................................543

16.7.19ASRC对C低部分的理想比率(ASRC_ASRIDRLC)...................................................................................548

16.7.3ASRC通道号配置寄存器（ASRC_ASRCNCR）..................................................................530

16.5.1.1

16.7.12对x的ASRC数据输入寄存器（ASRC_ASRDIn）.....................................................................................545

16.7.21ASRC56kHz以ASRC处理时钟(ASRC_ASR56K)表示的周期...........................550

16.7.23A对的ASRCFIFO状态寄存器（ASRC_ASRFSTA）...................................................................................553

过滤器的操作................................................................................................................................517

16.7.5ASRC时钟源寄存器(ASRC_ASRCSR).....................................................................................................534

16.7.14ASRC对A高部分的理想比率(ASRC_ASRIDRHA).....................................................................546

物理时钟的支持.........................................................................................517

16.7.7ASRC时钟分频器寄存器2(ASRC_ASRCDR2).....................................................................................538

16.7.16ASRC对B高部分的理想比率(ASRC_ASRIDRHB)...................................................................................547

i.MX6ULL应用处理器参考手册，修订版1，11/2017

16.7.18ASRC对C高部分的理想比率(ASRC_ASRIDRHC)...................................................................................548

16.7ASRC内存映射/寄存器定义.......................................................................................................................523

16.7.9ASRC参数寄存器n(ASRC_ASRPMnn).....................................................................................542

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恩智浦半导体

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40位纠错ECC加速器(BCH)

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第17章

17.6.2

16.7.25B对的ASRCFIFO状态寄存器（ASRC_ASRFSTB）.....................................................................556

Flash页面布局..........................................................................................................................................................567

17.3内存到内存（环回）操作.......................................................................................................................572

17.5复位期间的行为..........................................................................................................................................................592

17.4.1NAND写入的BCH编码.......................................................................................................................573

16.7.27C对的ASRCFIFO状态寄存器（ASRC_ASRFSTC）.....................................................................559

确定设备的ECC布局..........................................................................................................................569

硬件BCHECC加速器控制寄存器(BCH_CTRLn).....................................................................597

17.2.3

17.4.1.2使用BCH编码器.........................................................................................................................581

17.2.4

17.2.3.24K+128flash，10字节元数据，1024字节数据块，单独的元数据，假设

17.1概述...............................................................................................................................................................................563

17.4.2.1DMA结构代码示例......................................................................................................................586

17.6.1

16.7.24B对的ASRC杂项控制寄存器（ASRC_ASRMCRB）...........................................................554

17.2.1BCH限制和假设.......................................................................................................................................566

系统内存中的数据缓冲区.............................................................................................................................570

中断................................................................................................................................................591

17.2.2

16.7.26C对的ASRC杂项控制寄存器（ASRC_ASRMCRC）.....................................................................557

17.4编程BCH/GPMI接口........................................................................................................................................................573

17.6BCH内存映射/寄存器定义..........................................................................................................................593

硬件ECC加速器状态寄存器0(BCH_STATUS0n)..................................................................599

16.7.28X对的ASRC杂项控制寄存器1(ASRC_ASRMCR1n).....................................................................560

17.2.3.14K+218flash，10字节元数据，512字节数据块，独立元数据，假设

17.4.1.1DMA结构代码示例......................................................................................................................576

i.MX6ULL应用处理器参考手册，修订版1，11/2017

广发(213).............................................................................................................................569

17.4.2NAND读取的BCH解码..............................................................................................................582

17.4.3

17.4.2.2使用解码器................................................................................................................................589

17.2操作...................................................................................................................................................................565

GF(213)用于数据，GF(214)用于元数据...........................................................................570

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恩智浦半导体18

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第18话

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时钟控制器模块(CCM)

17.6.18ChienSearch调试读取寄存器(BCH_DBGCSFEREADn)......................................................................619

17.6.4

17.6.11硬件BCHECC闪存1布局1寄存器（BCH_FLASH1LAYOUT1n）...................................................609

17.6.8

18.3CCM时钟树...................................................................................................................................................................628

17.6.20总线主控器和ECC控制器调试读取寄存器(BCH_DBGAHBMREADn)...............................................620

硬件BCHECC环回编码缓冲寄存器(BCH_ENCODEPTRn)................................................602

17.6.13硬件BCHECC闪存2布局1寄存器(BCH_FLASH2LAYOUT1n)..................................................612

17.6.22BCH版本寄存器（BCH_VERSIONn）........................................................................................................621

18.1概述.............................................................................................................................................................................625

i.MX6ULL应用处理器参考手册，修订版1，11/2017

17.6.15硬件BCHECC闪存3布局1寄存器（BCH_FLASH3LAYOUT1n）...................................................615

17.6.5

特征............................................................................................................................................................625

硬件BCHECC环回元数据缓冲寄存器(BCH_METAPTRn).................................................603

18.2外部信号................................................................................................................................................................⋯⋯⋯⋯628

硬件BCHECC闪存0布局0寄存器(BCH_FLASH0LAYOUT0n)................................................604

17.6.17KES调试读取寄存器(BCH_DBGKESREADn).....................................................................................618

17.6.7

17.6.3

17.6.10硬件BCHECC闪存1布局0寄存器（BCH_FLASH1LAYOUT0n）...................................................607

17.6.19综合症发生器调试读取寄存器（BCH_DBGSYNDGENREADn）..................................................619

硬件ECC加速器模式寄存器(BCH_MODEn).........................................................601

17.6.12硬件BCHECC闪存2布局0寄存器（BCH_FLASH2LAYOUT0n）...................................................610

17.6.21块名称寄存器（BCH_BLOCKNAMEn）...........................................................................620

17.6.9

硬件BCHECC环回数据缓冲寄存器(BCH_DATAPTRn)....................................................602

17.6.14硬件BCHECC闪存3布局0寄存器（BCH_FLASH3LAYOUT0n）...................................................613

17.6.23硬件BCHECC调试寄存器1(BCH_DEBUG1n).....................................................................622

18.1.1

18.4系统时钟.....................................................................................................................................................................................630

17.6.6

18.1.2CCM框图........................................................................................................................................626

硬件ECC加速器布局选择寄存器(BCH_LAYOUTSELECTn)......................................603

17.6.16硬件BCHECC调试寄存器0(BCH_DEBUG0n).....................................................................616

硬件BCHECC闪存0布局1寄存器(BCH_FLASH0LAYOUT1n)................................................606

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18.5.1.5.2PLL旁路程序.....................................................................................649

时钟生成................................................................................................................................................643

18.5.1.3.3系统PLL............................................................................................................645

18.5.1.7时钟切换多路复用器......................................................................................................................652

退出等待模式...........................................................................................656

18.5.1.5.4时钟根发生器.....................................................................................649

18.5.1.9MMDC握手.......................................................................................................................654

18.5.1.1.1CKIL同步到IPG_CLK...................................................................................644

18.5.1.3.5

由系统JTAG控制器(SJC)控制的初始值......................................651

18.5.3

18.5.3.2.2

18.5.1.4相位小数分频器(PFD).....................................................................................................646

分频器更改握手...........................................................................651

18.5.3.1运行模式..............................................................................................................................655

18.5.1.3PLL参考时钟.......................................................................................................................................644

........................................................................................656进入等

待模式

18.5.1.1

18.5.1.5.1时钟切换器........................................................................................................647

禁用/启用PLL..........................................................................................................................651

18.5功能说明.....................................................................................................................................................................643

18.5.1.3.2USBPLL..............................................................................................................645

18.5.1.5.3PLL时钟变化.....................................................................................649

外部低频时钟‑CKIL.....................................................................................643

18.5.1.3.4音频/视频PLL................................................................................................645

18.5.1.5.5

18.5.1.8低功耗时钟门控模块(LPCG).....................................................................................653

i.MX6ULL应用处理器参考手册，修订版1，11/2017

18.5.2DVFS支持..........................................................................................................................................655

18.5.1.2外部高频时钟‑CKIH和内部振荡器......................................................644

以太网PLL......................................................................................................646

18.5.1.5.6

电源模式................................................................................................................................................655

18.5.3.2.1

18.5.1.6

18.5.3.2等待模式..........................................................................................................................656

18.5.1

18.5.1.5CCM内部时钟生成......................................................................................................646

18.5.1.3.1ARM锁相环.....................................................................................................⋯⋯⋯⋯644

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18.6.14CCMHSC时钟分频器寄存器（CCM_CHSCCDR）.....................................................................................681

进入停止模式...........................................................................................657

18.6.7CCM总线时钟多路复用器寄存器(CCM_CBCMR)...................................................................................669

18.6.23CCM时钟门控寄存器0(CCM_CCGR0)................................................................................................698

18.6.16CCM串行时钟分频器寄存器3(CCM_CSCDR3)...................................................................................684

18.6.25CCM时钟门控寄存器2(CCM_CCGR2).....................................................................................702

18.6CCM存储器映射/寄存器定义..........................................................................................................................658

18.6.9CCM串行时钟多路复用器寄存器2(CCM_CSCMR2).....................................................................673

18.6.18CCM低功耗控制寄存器(CCM_CLPCR).....................................................................................688

18.5.3.3.2

18.6.11CCMSAI1时钟分频器寄存器(CCM_CS1CDR).....................................................................................676

18.6.20CCM中断屏蔽寄存器(CCM_CIMR)......................................................................................................693

18.6.2CCM控制分频寄存器(CCM_CCDR).....................................................................................................661

18.6.4CCM时钟切换寄存器(CCM_CCSR).....................................................................................................664

18.6.13CCMD1时钟分频器寄存器(CCM_CDCDR)...................................................................................680

18.6.22CCM通用寄存器（CCM_CGPR）................................................................................................697

18.5.3.3停止模式..........................................................................................................................657

18.6.6CCM总线时钟分频寄存器(CCM_CBCDR).....................................................................................666

18.6.15CCM串行时钟分频器寄存器2(CCM_CSCDR2)...................................................................................682

退出停止模式.........................................................................................................657

18.6.8CCM串行时钟多路复用器寄存器1(CCM_CSCMR1).....................................................................670

18.6.17CCM分频器握手进行中寄存器（CCM_CDHIPR）...........................................................685

18.6.24CCM时钟门控寄存器1(CCM_CCGR1).....................................................................................700

18.5.3.3.1

18.6.1CCM控制寄存器(CCM_CCR)........................................................................................................................660

18.6.10CCM串行时钟分频器寄存器1(CCM_CSCDR1)...................................................................................674

18.6.19CCM中断状态寄存器（CCM_CISR）......................................................................................................690

i.MX6ULL应用处理器参考手册，修订版1，11/2017

18.6.21CCM时钟输出源寄存器(CCM_CCOSR).....................................................................................695

18.6.3CCM状态寄存器（CCM_CSR）........................................................................................................................663

18.6.12CCMSAI2时钟分频器寄存器(CCM_CS2CDR).....................................................................................678

18.6.5CCMArm时钟根寄存器(CCM_CACRR)...................................................................................................665

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