Xilinx Vivado HLS：高阶综合指南与设计优化

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Vivado High-Level Synthesis (HLS)是Xilinx Vivado Design Suite的一部分，专注于将高级语言（如C）编写的算法转化为硬件设计，旨在简化FPGA和ASIC设计过程。该指南（UG902 v2014.1）于2014年4月发布，更新了Vivado Design Suite用户手册中的HLS内容组织，并引入了名为HLS UltraFast Design Methodology的新方法论。第1章详细介绍了HLS的基本概念，包括如何利用基于C的编程进行FPGA设计。它涵盖了如何在Vivado HLS环境中工作，从编写C代码到实现高性能、低延迟的设计。这部分还讨论了接口管理、设计优化策略以及如何通过RTL Verification确保代码的质量，以及如何最终导出硬件描述语言（RTL）设计。第2章着重于使用Vivado HLS库，这些库为特定应用提供了预定义的功能和数据类型，例如Arbitrary Precision DataTypes Library用于处理高精度数据，HLS Stream Library支持流处理，HLS Math Library提供数学运算功能，Vivado HLS Video Library专为视频处理设计，而IPLibraries（Image Processing Libraries）则针对图像处理任务。另外，还有HLS Linear Algebra Library，便于执行线性代数计算。第3章探讨了在HLS编程时需要注意的一些限制和最佳实践，如不支持的C构造、如何创建有效的测试平台（CTestBench），以及函数的使用方式。这些指导有助于开发者编写高效且可转换的代码，避免在HLS转换过程中遇到的问题。 Vivado HLS是一个强大的工具，它允许工程师使用熟悉的C语言开发，同时利用Xilinx的优化算法将代码自动映射到硬件上。通过理解并遵循指南中的内容，设计师可以提升设计效率，缩短开发周期，并在满足性能需求的同时，降低硬件复杂度。随着技术的发展，后续版本可能会包含更多优化方法和库，以适应不断变化的需求。

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UG902 (v2014.1) April 2, 2014

Chapter 1: High-Level Synthesis

In addition, Vivado HLS provides several C libraries to extend the standard C languages. C

libraries contain functions and constructs which have been optimized for implementation

on an FPGA and help ensure the final output is a design with high Quality-of-Results (QoR):

a high-performance design and with optimal use of the resources. Because the libraries are

provided in C, C++ or SystemC they can be incorporated into the C function and simulated

to verify the functional correctness before synthesis.

C libraries are provided for:

• Arbitrary Precision data types.

•Math operations.

• Video functions.

• Xilinx IP functions (FFT and FIR).

• FPGA resource functions (help maximize the use of SRL resources)

An examination of the arbitrary precision data type libraries helps demonstrate why these

libraries are useful in creating designs with high QoR.

Standard C types are based on 8-bit boundaries (8-bit, 16-bit, 32-bit, 64-bit). When

targeting a hardware platform it is often more efficient to use data types of a specific width.

For example, assume the design to be created is a filter function for a communications

protocol which only requires 10-bit input data and 18-bit output data to satisfy the data

transmission requirements. Using standard C data types would require the input data be at

least 16-bits and the output data to be at least 32-bits. In the final hardware this would also

create a datapath between the input and output which is wider than it needs to be, uses

more resources, has longer delays (an 18-bit by 18-bit multiplication completes in less time

than a 32-bit by 32-bit multiplication) and requires more clock cycles to complete.

Using arbitrary precision data types allows the exact bit-sizes to be specified in the C code

prior to synthesis and the updated C code to be simulated and the quality of the output

verified by C simulation prior to synthesis.

IMPORTANT: Arbitrary precision data types ensure the C code can be simulated with the exact bit-sizes

desired in the final hardware implementation and the results verified before synthesis.

Arbitrary precision types are only required on the function boundaries, as Vivado HLS

optimizes the internal logic and remove any data bits and logic which do not fanout to the

output ports. To use the debugging operations in the C code it is recommended to update

all data types in the C code that are required to be arbitrary precision types. The designer

converts from one data size to the next in their head during the debug process: let the C

compiler do the work.

Arbitrary precision data types are provided for C and C++ and allow data types of any width

from 1 to 1024-bit to be modeled (Some C++ types can be modeled up to 32768 bits). More

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UG902 (v2014.1) April 2, 2014

Chapter 1: High-Level Synthesis

details on arbitrary precision data types can be found in the Data Types for Efficient

Hardware section.

More information on the C libraries provided by Vivado HLS is provided in the Video

Functions Reference section.

Synthesis, Optimization and Analysis

Vivado HLS is project based. Each project holds one set of C code. Each project can contain

multiple solutions. Each solution might have different constraints and optimization

directives. The results from each solution can be compared to one another from within the

Vivado Integrated Design Environment (IDE).

The HLS design process is to create a project with an initial solution, verify the C simulation

executes without error and run synthesis to obtain an initial set of results. Then after

analysis of the results, create a new solution with the project with different constraints

and/or optimizations specified, synthesize the new solution and repeat this process until

the design has the desired performance characteristics. Using multiple solutions allows

development to proceed without losing any of the previous results.

Vivado HLS provides several optimizations which can be applied to the design. Some

examples of these are:

• Specify a specific latency for the completion of functions, loops, and regions.

• Specify a limit on the number of resources used.

• Instruct a task to execution in a pipelined manner, allowing the next execution of that

task to begin before the current execution has completed.

• Override the inherent or implied dependencies in the code and permit operations. For

example, if the initial data values can be discarded or ignored, as in a video stream,

allow a memory read before write if it results in more optimal performance.

Optimizations can be specified directly from the Vivado IDE by referencing objects in the

source code. The Design Optimization section provides more details on the various

optimizations which can be performed on the design.

RECOMMENDED: It is highly recommended to review the HLS UltraFast Design Methodology section on

methodology before applying optimizations to the design.

Also to optimizations on the logic structures and behavior, Vivado HLS supports

optimizations for the RTL design ports.

The arguments of the top-level function to be synthesized are implemented as I/O

(input-and-output) ports in the final RTL design. Optimization directives allow these I/O

ports to be implemented with a selection of I/O protocols. The I/O protocol should be

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UG902 (v2014.1) April 2, 2014

Chapter 1: High-Level Synthesis

Verifying the RTL is Correct

After synthesis, the Vivado HLS RTL verification feature can be used to verify the RTL.

If a C test bench was added to the project it can be used to verify the RLT is functionally

identical to the original C.

IMPORTANT: The verification of the results is performed by the C test bench.

The C test bench should verify the output from the function chosen as the top-level for

synthesis and return 0 (zero) to the top-level function main() if the results are correct. This

return value is used in both C simulation and C/RTL cosimulation to determine if the results

are correct. If any non-zero value is returned, the simulation is considered to have failed.

Even if the output data is correct and valid, Vivado HLS reports a simulation failure if the

test bench does not return the value zero to function main().

All of the example designs discussed in the Design Examples and References section have

test benches operating in this manner and can be used as references.

Vivado HLS automatically creates the infrastructure to perform the C/RTL cosimulation and

automatically executes the simulation using one of the supported RTL simulators:

• Vivado Simulator

•Questa SIM

•VCS

•NCSim

•ISim

• Riviera

• Open SystemC Initiative (OSCI)

If the Hardware Description Languages (HDLs) Verilog or VHLD are selected for simulation,

the selected HDL simulator is used: the HDL simulator requires a license from the

appropriate vendor (The Xilinx design tools include Vivado Simulator and ISim). The VCS,

NCSim, and Riviera HDL simulators are only supported on the Linux operating system.

The SystemC RTL output can be verified using the built-in SystemC kernel and does not

require a third-party simulator or license.

Additional details on this step are available in the Using C/RTL Cosimulation section.

Using the Output from Vivado HLS

The RTL Export feature is used to package the final RTL output files as IP. The IP can be

packaged in one of five Xilinx IP formats:

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