BK2461L：集成FLIP51处理器的低功耗RF SOC芯片详情

需积分: 7 47 浏览量更新于2024-06-28 收藏 3.59MB PDF 举报

BK2461L是一款由Beken Corporation开发的高性能RF系统-on-chip (RF SOC) 芯片，它集成了最新的FLIP51处理器。这款设备专为2.4GHz遥控应用设计，具备以下主要特点： 1. **电源管理**：BK2461L支持1.9V到3.6V的宽电压输入范围，适用于各种低功耗应用场景。 2. **处理器兼容性**：作为8051架构的升级版，FLIP51 MCU提供了强大的处理能力，其4阶段流水线架构允许大部分指令在一个时钟周期内完成，提高了执行效率。 3. **存储器**：芯片内置8k字节的只读一次可编程存储器(OTP)用于程序存储，以及256字节的内部RAM和512字节的静态随机存取内存(SRAM)，确保了足够的数据存储空间。 4. **定时器/计数器**：嵌入式三个定时器/计数器模块，为精确的时间管理提供了灵活性。 5. **通信接口**：支持UART和I2C通信接口，方便与外部设备进行数据交换。 6. **GPIO引脚**：总共提供9个或18个通用输入/输出引脚，满足多种功能扩展的需求。 7. **PWM输出**：最多支持5路PWM信号，可用于电机控制、信号调制等应用。 8. **实时调试**：集成的BIRD（ Built-In Real-time Debugger）功能，便于硬件调试和软件开发。 9. **版本更新**：该文档列出了不同版本的历史，包括0.1到0.6版本，展示了持续的改进和优化，如睡眠模式下的功耗管理和功能增强。 10. **文档保密性**：文档内容属于Beken Corporation的专有和机密信息，未经许可不得随意外泄。 11. **技术支持**：Beken Corporation提供了专业技术指导热线13662648446，用户在使用过程中遇到问题可以寻求帮助。 BK2461L凭借其高性能、低功耗和丰富的功能集，适合于对无线通信性能要求高的嵌入式系统设计，例如遥控器、传感器网络或者物联网应用中的节点。通过深入了解其架构和特性，开发者可以更有效地利用此芯片来构建高效能的解决方案。

BK2461

5.2 MCU diagram

Figure 5 FlIP51 architecture

专业技术指导：13662648446

BK2461

Registers R0 and R1 indirectly address external data memory locations 00h-FFh. When

MOVX instructions use this indirect mode, the MSB of the 16-bit address is filled with

the content of MPAGE SFR (0A1h). Then, it allows MOVX @Ri instruction to access to

64K Bytes of external data memory. Usually, in 80C51 application, the Port 2 is used to

this address extension. In order to keep software compatibility with existing 80C51

program, the register MPAGE is also updated by any value written at P2 register.

-bit data pointer (@DPTR).

The MOVX instructions use these indirect modes to access the page of the external data

RAM pointed by the extended data pointer (DPX).

7.4 Internal Data Memory (IDATA space)

The Internal data memory is composed by 256 bytes of internal RAM and by a

number of SFRs.

The main difference between these IDATA and XDATA spaces is the kind of

instructions that enable to access to these memories. Most of the “data transfer”

instructions are dedicated to access internal data memory (IDATA) since there are only

four instructions (MOVX) dedicated to access external data memory. Moreover, only

indirect addressing mode is available for XDATA whilst IDATA can be addressed by

flexibility to access data. In addition, the Flip8051 memory interface with IDATA space

is optimized and then access time to this space is faster than the access time of XDATA

for both read/write operations.

7.4.1 Internal Data memory organization

The internal data memory is divided into 3 spaces, which are referred to as the Lower 128,

Upper 128 and SFR space. Either direct or indirect addressing may be used to access the

lower 128 bytes of internal data memory. The upper 128 bytes of internal data memory are

accessible by indirect addressing only while direct addressing to region above 0x7F will

access SFR space.

In the Flip8051, the SFRs are implemented internally to the model using Flip-Flops.

专业技术指导：13662648446

BK2461

Figure 7 Internal Data memory

7.4.2 Internal ram: lower 128 byes

Figure 8 Internal Ram lower 128 bytes

The lower 128 bytes of Internal Data Memory is organized in three distinct areas:

0x00-0x1F: The Register Banks are at the lowest 32 bytes of the internal data memory. Only

one Register Bank is used at a time when an instruction uses R0 to R7. 2 bits in Processor

Status Word (PSW), called RS1 and RS0, control the selection of the Register Bank. Bank 0

is selected upon reset. Indirect addressing mode used R0 and R1 as index registers

0x20-0x2F: This memory space contains a general-purpose memory, which is bit addressable

as well as byte addressable. The bit address ranged from 0 to 0x7F. When bit addressing is

used in an instruction, the bit access in this region will occur. In this memory range, when bit

addressing is used, bit address 0x00 is the bit 0 of address 0x20 while bit 7 of of the byte

0x20 has bit address 0x07. Bit address 0x7F is the bit 7 of address 0x2F. A bit access is

different than a byte access by the type of instruction used.

0x30-0x7F: A general-purpose byte-addressable memory is located above address 0x30. It

can be accessed both by direct or indirect addressing mode.

7.4.3 Internal Ram: Upper 128 Bytes

The usage of the addresses between 0x80 and 0xFF is up to the user. This memory can be

used for any purpose providing that indirect addressing mode is used when accessing this

memory space, otherwise the Special Function Register memory will be accessed.

7.4.4 The Stack and the stack pointer

The stack refers to an area of internal RAM that is used in conjunction with certain

instructions (PUSH, POP) to store and retrieve data quickly. The Stack pointer register (SP,

0x81) is used to hold an internal RAM address that is called the “top of the stack”. The data

held in the SP register is the address in internal RAM where the last byte of data was stored

by a stack operation. The reset value of Stack pointer register is 0x07 and can be changed to

any internal RAM address by the programmer. Usually, the stack is located high in the RAM

to avoid conflict with the work register, bit and byte area in internal RAM.

专业技术指导：13662648446

剩余95页未读，继续阅读

V13662648446

粉丝: 55
资源: 14

BK2461L：集成FLIP51处理器的低功耗RF SOC芯片详情

BK2461L Datasheet v0.6.pdf

BK3296， Datasheet规格书-V0.4.pdf

BK3433， Datasheet规格书-V0.71.pdf

BK2451，Datasheet v1.3(1).pdf

BK3437 Datasheet-V1.0.pdf

BK3433 Datasheet_V0.7(1).pdf

BK3432, Datasheet.pdf

BK7258 Datasheet-V1.4.pdf-规格书

BK7238 Datasheet-V1.3.pdf-物联网芯片规格书

BK3432 Datasheet.pdf

最新资源