Vol. 36, No. 3 Journal of Semiconductors March 2015
A novel high figure-of-merit SOI SJ LDMOS with ultra-strong charge
accumulation effect
Tian Ruichao(田瑞超), Luo Xiaorong(罗小蓉)
, Zhou Kun(周坤), Xu Qing(徐青), Wei Jie(魏杰),
Zhang Bo(张波), and Li Zhaoji(李肇基)
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology
of China, Chengdu 610054, China
Abstract: A novel silicon-on-insulator (SOI) super-junction (SJ) LDMOS with an ultra-strong charge accumula-
tion effect is proposed. It has two key features: an assisted-accumulation trench-type extending gate (TEG) with a
high-k (HK) dielectric and a step-doped N pillar (TEG-SD SJ LDMOS). In the on-state, electrons accumulate at
the sidewall of the HK dielectric from the source to the drain by the TEG. Furthermore, the high permittivity of the
HK dielectric leads to an ultra-strong charge accumulation effect. As a result, an ultra-low resistance current path is
formed. The specific on-resistance (R
on; sp
/ is thus greatly reduced and is independent of the drift doping concentra-
tion. In the off-state, the step-doped N pillar effectively suppresses the substrate-assisted depletion effect by charge
compensation. Moreover, the reshape effect of the HK dielectric and the new electric field (E-field) peak introduced
by the step-doped N pillar enhance the drift region E-field. Hence, the BV is improved. Simulation indicates that
the TEG-SD SJ LDMOS achieves an extremely low R
on; sp
of 1.06 mcm
2
and a BV of 217 V. Compared with the
conventional SJ LDMOS, the TEG-SD SJ LDMOS decreases the R
on; sp
by 77.5% and increases the BV by 33%,
exhibiting a high figure of merits (FOM D BV
2
/R
on; sp
/ of 44 MW/cm
2
.
Key words: charge accumulation effect; super junction; breakdown voltage; specific on-resistance
DOI: 10.1088/1674-4926/36/3/034007 EEACC: 2560; 2560P
1. Introduction
For the lateral double-diffusion MOSFET (LDMOS), one
of the major issues is the trade-off between the breakdown
voltage (BV) and the specific on-resistance (R
on; sp
/
Œ13
. The
trench gate
Œ4; 5
and super-junction (SJ) technology have been
widely adopted to alleviate this contradiction. However, the
conventional SJ LDMOS (Con. SJ LDMOS) suffers from the
substrate-assisted depletion (SAD) effect
Œ6
. To address this is-
sue, several structures have been developed
Œ711
. The reshape
effect of the high-k (HK) dielectric can enhance the drift region
electric field (E-field) to improve the BV
Œ1214
. Nevertheless,
the R
on; sp
of the aforementioned LDMOSFETs still strongly
depends on the doping concentration of the drift region. An
extended-gate LDMOS has been reported, which uses the gate
to enhance the conductivity of the drift region
Œ15
. However,
it has an intrinsic high gate leakage current under high-gate-
voltage applications and the carrier accumulation layer only
exists at the surface of the drift region.
In this paper, we propose a novel silicon-on-insulator
(SOI) SJ LDMOS with an assisted-accumulation trench-type
extending gate (TEG) and a step-doped N pillar (TEG-SD SJ
LDMOS). The TEG forms the electrons accumulation layer
at the sidewall of the high-k dielectric. The on-state current
predominantly flows along the accumulation layer. Accord-
ingly, the R
on; sp
sharply decreases and is almost independent
of the drift region doping concentration. Besides, the high gate
leakage current in Reference [15] is eliminated by the built-in
reverse-biased diode. In the off-state, the step-doped N pillar
effectively alleviates the SAD effect. The reshape effect of the
high-k dielectric and the new E-field peak further enhance the
drift region average E-field. Therefore, the TEG-SD SJ LD-
MOS not only improves the BV but also reduces the R
on; sp
.
2. Structure and mechanism
Figure 1(a) is the three-dimensional schematic structure of
the TEG-SD SJ LDMOS. The TEG consists of the P pillar and
the surrounding HK dielectric. The TEG is inserted in the N-
drift region and forms an SJ structure with the N-drift region
(N pillar). The P
C
region in the TEG is connected to the gate
electrode (G). Diodes D1 and D2 in the TEG are integrated
near the drain. Furthermore, the D1 is connected to the drain
electrode (D). Thereby, the D1 and D2 sustain the gate–drain
voltage (V
GD
/ in the on-state and off-state, respectively. The N
pillar is divided into two doping regions. The doping concen-
tration (N
D
/ of the N pillar close to the source (N
0
region) is
the same as that of the P pillar (N
A
/. The N pillar near the drain
(N
1
region) is doped with a higher doping concentration (N
n
/,
i.e. N
n
D N C N
D
.
Figure 1(b) shows the cross section along the AA
0
plane
and schematic electron distribution. Figure 1(c) shows the
equivalent resistances and the equivalent metal–insulator–
semiconductor (MIS) capacitance consisting of the P pillar/HK
* Project supported by the National Natural Science Foundation of China (Nos. 61176069, 61376079) and the Program for New Century
Excellent Talents in University of Ministry of Education of China (No. NCET-11-0062).
† Corresponding author. Email: xrluo@uestc.edu.cn
Received 5 August 2014, revised manuscript received 18 September 2014 © 2015 Chinese Institute of Electronics
034007-1