TVP5146芯片技术手册：2003年9月版

TVP5146芯片资料

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"TVP5146芯片是Texas Instruments（TI）公司生产的一款数字视频解码器，常用于处理模拟视频信号并将其转换为数字格式。这款芯片在各种音频视频应用中表现出色，如高清电视、监控系统以及多媒体设备等。TVP5146的详细资料包括其功能特性、接口规格、操作指南以及相关的硬件和软件配置信息。 TVP5146芯片的主要功能是将模拟复合视频或分量视频信号转换为数字视频流。它支持多种视频标准，如NTSC、PAL和SECAM，能够提供高质量的视频解码效果。芯片内部集成了视频解码、梳状滤波、色彩空间转换等功能，以确保输出的数字视频数据准确无误。在接口方面，TVP5146通常配备有模拟视频输入接口，如CVBS（复合视频基带信号）和YUV（分量视频）接口，同时可能还包含数字串行接口如SPI或I2C，用于与主机处理器通信。此外，它可能还具备数字视频输出接口，如LVDS（低压差分信号）或者SDI（串行数字接口），以适应不同的系统需求。数据手册（HPA Digital Audio Video Data Manual SLES084）提供了关于TVP5146的详细技术参数和操作指导，包括电气特性、电源要求、物理尺寸、引脚定义、时序图以及应用电路示例。这份文档对于设计者来说是极其重要的参考资料，可以帮助他们正确地集成TVP5146到他们的系统中。 TI强调，虽然他们会按照标准保修条款对产品性能进行保证，但产品的具体表现可能会因使用环境和条件的不同而有所差异。他们可能随时对产品进行改进、增强或停止生产，且不一定会提前通知。因此，购买和使用TVP5146的用户应当确保获取最新的技术信息，并且在下单前确认这些信息的准确性和完整性。在使用TVP5146时，开发人员需要遵循TI提供的销售条款和条件，同时考虑到可能的政府法规要求。TI不会为意外情况或未经过充分测试的参数设置导致的问题承担法律责任。因此，在实际应用中，对所有产品的全面测试和验证是至关重要的，以确保系统的稳定性和可靠性。总结来说，TVP5146是一款强大的数字视频解码芯片，广泛应用于各种视频处理场景。要充分利用其功能，开发者必须仔细阅读并理解TI提供的详细资料，包括数据手册和相关文档，确保产品在设计和使用过程中满足预期的性能和兼容性要求。"

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2−1

2 Functional Description

2.1 Analog Processing and A/D Converters

Figure 2−1 shows a functional diagram of the analog processors and ADCs. This block provides the analog interface

to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A/D

conversion, and gain and offset adjustments to center the digitized video signal.

Clamp

PGA

10-Bit

ADC

CH4 A/D

PGA

CH1 A/D

PGA

CH2 A/D

PGA

CH3 A/D

Line-Locked Sampling Clock

TVP5146 Analog Front End

VI_4_A

VI_1_A

VI_1_B

VI_1_C

VI_2_A

VI_2_B

VI_2_C

VI_3_A

VI_3_B

VI_3_C

10-Bit

ADC

10-Bit

ADC

10-Bit

ADC

Clamp

Figure 2−1. Analog Processors and A/D Converters

2.1.1 Video Input Switch Control

The TVP5146 decoder has 4 analog channels that accept up to 10 video inputs. The user can configure the internal

analog video switches via I

C. The 10 analog video inputs can be used for different input configurations, some of

which are:

• Up to 10 selectable individual composite video inputs

• Up to four selectable S-video inputs

• Up to three selectable analog YPbPr/RGB video inputs and one CVBS input

• Up to two selectable analog YPbPr/RGB video inputs, two S-video inputs, and two CVBS inputs

The input selection is performed by the input select register at I

C subaddress 00h (see Section 2.11.1).

2−2

2.1.2 Analog Input Clamping

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides

line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid

clamp is performed automatically by the TVP5146 decoder.

2.1.3 Automatic Gain Control

The TVP5146 decoder utilizes four programmable gain amplifiers (PGAs); one per channel. The PGA can scale a

signal with a voltage-input compliance of 0.5-V

to 2.0-V

to a full-scale 10-bit A/D output code range. A 4-bit code

sets the coarse gain with individual adjustment per channel. Minimum gain corresponds to a code 0x0 (2.0-V

full-scale input, −6-dB gain) while maximum gain corresponds to code 0xF (0.5 V

full scale, +6-dB gain). The

TVP5146 decoder also has 12-bit fine gain controls for each channel and applies independently to coarse gain

controls. For composite video, the input video signal amplitude may vary significantly from the nominal level of 1 V

The TVP5146 decoder can adjust its PGA setting automatically: an AGC can be enabled and can adjust the signal

amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video signals

contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back gain to avoid

clipping. If the AGC is on, then the TVP5146 decoder can read the gain currently being used.

The TVP5146 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C separation.

The back-end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak

(which is only relevant before Y/C separation) forces the front-end AGC to set the gain too low. The front-end and

back-end AGC algorithms can utilize up to four amplitude references: sync height, color burst amplitude, composite

peak, and luma peak.

The specific amplitude references being used by the front-end and back-end AGC algorithms can be independently

controlled using the AGC white peak processing register located at subaddress 74h. The TVP5146 gain increment

speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress

78h and the AGC increment delay register located at subaddress 79h, respectively.

2.1.4 A/D Converters

All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive an identical clock

from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages

are generated internally.

2.2 Digital Video Processing

Figure 2−2 is a block diagram of the TVP5146 digital video decoder processing. This block receives digitized video

signals from the ADCs and performs composite processing for CVBS and S-video inputs, YCbCr signal

enhancements for CVBS and S-video inputs, and YPbPr/RGB processing for component video inputs. It also

generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs.

Additionally, it can provide field identification, horizontal and vertical lock, vertical blanking, and active video window

indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external syncs or 10-bit

4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses, and color striping in

Macrovision-encoded copy-protected material. Information present in the VBI interval can be retrieved and either

inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO and/or registers for retrieval via the

host port interface.

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