DesignWare SATA AHCI Databook v2.00a - Synopsys

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"DesignWare Cores SATA AHCI Databook, Version 2.00a, September 2009" DesignWare Cores SATA AHCI Databook 是一份由Synopsys公司出版的重要技术文档，专注于介绍DesignWare SATA高级主机控制器接口（AHCI）的核心组件及其相关技术。该文档涵盖了与SATA接口和AHCI协议相关的详细信息，是设计和实现基于SATA存储解决方案的关键参考资料。 SATA（Serial Advanced Technology Attachment）是一种高速接口标准，用于连接计算机系统和存储设备，如硬盘驱动器、固态驱动器等。它提供了比并行ATA更高的数据传输速度，并支持热插拔和串行通信，以降低电磁干扰。 AHCI（Advanced Host Controller Interface）是一个硬件抽象层，允许操作系统与SATA控制器进行通信，支持诸如NCQ（Native Command Queuing）等高级功能，以优化硬盘性能。DesignWare SATA AHCI Core是Synopsys提供的IP核，旨在简化嵌入式系统和SoC设计中SATA接口的集成。在Databook中，读者可以找到以下关键知识点： 1. **技术规格**：详细描述了DesignWare SATA AHCI Core的电气特性、接口规范、时序要求等，包括其兼容的SATA速率（如3.0 Gbps, 6.0 Gbps等）。 2. **AHCI架构**：解释了AHCI接口如何通过内存映射I/O（MMIO）与主机处理器通信，以及如何管理命令列表和FIS（帧信息结构）来控制SATA设备。 3. **功能特性**：包括中断处理、错误处理机制、端口多路复用、NCQ支持、电源管理等高级功能。 4. **设计实例**：提供了实施示例，帮助设计师理解如何在实际项目中集成和配置DesignWare SATA AHCI Core。 5. **软件开发**：指导用户如何编写和调试驱动程序，以充分利用AHCI接口，包括中断处理程序、设备初始化、命令提交等。 6. **测试与验证**：包含了测试策略和方法，帮助确保DesignWare SATA AHCI Core在系统中的正确性和可靠性。 7. **合规性与认证**：讨论了符合行业标准（如PCI-SIG, SATA-IO）的要求，以及如何进行兼容性测试。 8. **许可证和版权信息**：强调了Synopsys对软件和文档的所有权，使用和复制需遵循特定的许可协议条款。请注意，由于法律限制，该文档中的技术数据可能受美国出口管制法规约束，读者有责任了解并遵守相关法规。 DesignWare Cores SATA AHCI Databook是设计人员和工程师开发支持SATA存储系统的宝贵资源，提供深入的技术细节和实用指南，帮助他们高效地构建高性能、可靠的存储解决方案。

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1.1 Overview

The DesignWare Cores SATA AHCI Core (commonly referred to as the DWC_ahsata), implements the

Serial Advanced Technology Attachment (SATA) storage interface for physical storage devices. This

product includes the DWC_ahsata coreKit that you use with coreConsultant to configure your specific

design implementation of the DWC_ahsata core.

For information on how to download and install the SATA AHCI, refer to the DesignWare Cores SATA AHCI

Installation Guide.

The following are features of the DWC_ahsata:

❖ Supports SATA 1.5 Gb/s, SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds (6.0 Gb/s speed requires

additional license)

❖ Supports eSATA

❖ Compliant with Serial ATA Specification 2.6, and AHCI Revision 1.3 specifications (except FIS-based

switching)

❖ Highly configurable PHY interface

❖ Provides additional user defined PHY status and control ports

❖ Optional Rx Data Buffer for recovered clock systems

❖ Optional data alignment circuitry when Rx Data Buffer is also included

❖ Optional OOB signaling detection and generation

❖ SATA 1.5 Gb/s, SATA 3.0 Gb/s, and SATA 6.0 Gb/s speed negotiation when Tx OOB signalling is

selected

❖ Asynchronous Signal Recovery, including retry polling, when Tx OOB signalling is included.

❖ Digitally supports device hot-plugging when Tx OOB signaling is included

❖ Optional 8b/10b encoding/decoding

❖ Supports power management features including automatic Partial to Slumber transition

❖ Supports BIST loopback modes

❖ Supports up to eight SATA devices (configurable from 1 to 8 ports)

❖ Configurable AMBA AHB or AXI interface (one master and one slave for each interface)

❖ Internal DMA engine per port

❖ Supports hardware-assisted Native Command Queuing for up to 32 entries

❖ Supports Port Multiplier with command-based switching

❖ Optional mechanical presence switch, cold presence detect, and activity LED support

❖ Supports disabling Rx and Tx Data clocks during power down modes

❖ Supports eSATA (external analog logic also needs to support eSATA)

Attention

See Note on page 79 regarding clock restoration requirements when clocks are removed during

power modes.

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The DWC_ahsata consists of three main blocks:

❖ Bus Interface Unit (BIU) — Overview provided in “Bus Interface/ Generic Register Overview” on

page 19, fully described in “Bus Interface Unit” on page 43

❖ Generic Register (GCSR) — Overview provided in “Bus Interface/ Generic Register Overview” on

page 19, fully described in “Generic Registers (GCSR)” on page 52.

❖ Ports(s) —Overview provided in “Port DMA and Register Modules Overview” on page 20, fully

described in “Port” on page 52.

The required number of Ports is set via coreConsultant during the core configuration resulting in multiple

Port instances running in parallel and independent of each other. Each Port contains its own DMA engine

that implements AHCI functionality and initiates all of the data transfers between the SATA device and

system memory.

The DWC_ahsata Port PHY interface operates in three or four clock domains (separate for each Port):

RxOOB clock (clk_rxoob), Rx clock (clk_rbc) when present, keep-alive clock (clk_pmalive) and Tx clock

(clk_asic). Most of the Link Layer (both receive and transmit data paths), and part of the Transport Layer

always operate in the Tx clock domain. The Rx clock is a clock recovered from the PHY, and is used for

clocking data into the DWC_ahsata. The Port contains a Power Control Module operating in the always-

alive pmalive clock domain. This Power Control Module facilitates disabling Rx and Tx clocks in power

down modes.

The system bus provides the application clock (hclk for AHB, aclk for AXI). BIU, GCSR and part of the Port

operate in the application clock domain. Its frequency is limited by the technology library and input/output

constraints. Rx (when present), and Tx clocks are generated in the PHY and depend on the interface speed

and PHY data width, as shown in Table 1-1. The optional Rx OOB clock frequency can be set by the user (see

“Link Layer” on page 21 for more details).

All DWC_ahsata clocks are asynchronous to each other in general. The BIU connects Ports to the system

bus. The AMBA master interface is used to transfer data between the Ports and the system memory, while

the AMBA slave interface is used by the software (driver) to access DWC_ahsata registers. All the

DWC_ahsata global registers are implemented in the Generic Register module.

Table 1-1 PHY-Supplied Clock Frequencies (clk_rbc and clk_asic)

Interface

Speed (Gb/s)

PHY-Supplied Clock Frequencies (Mhz)

8/10 bits 16/20 bits 32/40 bits

1.5 150 75 37.5

3.0 300 150 75

6.0

300 150

When PHY_DATA_WDITH == 1, the core is limited to 3.0 Gb/s speed unless synthesis can meet timing

at 600 MHz in the clk_asic and clk_rbc clock domains.

September 2009 Synopsys, Inc. 19

SATA AHCI Databook Product Overview

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1.3.2 DWC_ahsata Transfer Hierarchy

Figure 1-3 shows the DWC_ahsata transfer hierarchy from the system bus point of view.

Figure 1-3 DWC_ahsata Transfer Hierarchy

Data for an ATA/ATAPI command resides in the system memory in the form of one or more Physical

Region Descriptors (PRD). PRD entries describe the physical location and length of data to be transferred.

Each PRD entry is read by the DWC_ahsata Port DMA from the system memory before transferring the

block of data associated with this entry.

The Port DMA transfers the PRD data block between the system memory and its FIFOs using one or more

DMA transactions. DMA transaction size can be set by software independently for each Port.

Finally, the BIU Master generates one or more AHB or AXI burst or single bus transfers based on the DMA

transaction request from the PDMA. The BIU Master tries to generate the burst equal to the DMA

transaction size, but it might break it into several burst/single transfers due to various bus conditions (i.e.

early burst termination, 1KB (AHB) or 4KB (AXI) address boundary crossing, etc.).

1.3.3 Bus Interface/ Generic Register Overview

The Bus Interface provides the following functions:

❖ Transfers data between the Ports and system memory using AHB or AXI master interface;

❖ Arbitrates between the multiple active Ports using equal-priority/round-robin scheme. Each active

Port takes turns accessing system memory on a DMA transaction basis.

❖ Provides access to DWC_ahsata registers using AHB or AXI slave interface.

The AHB interface has the following features:

❖ Compliant with ARM AMBA

specification rev. 2.0

❖ Supports little-endian or big-endian byte ordering

❖ Supports 32-bit data and 32- or 64-bit address bus width

NoteNoteNoteNote

Since the transaction size is programmable for each Port, system software can change a Port’s

priority by varying it’s transaction size - the Port with a bigger transaction size would have higher

priority than the one with a smaller size.

ATA/ATAPI Command Transfer

Physical Region Descriptor (PRD) Physical Region Descriptor (PRD)

. . .

. . . . . .

DMA Transaction DMA TransactionDMA Transaction DMA Transaction

AMBA

Single

Transfer

AMBA

Burst

Transfer

AMBA

Single

Tra nsfe r

AMBA

Burst

Tra nsfe r

AMBA

Single

Transfer

AMBA

Burst

Transfer

AMBA

Single

Transfer

AMBA

Burst

Transfer

. . . . . . . . . . . .

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❖ Master supports 32-bit (burst/single) and 16-bit (single only) transfer sizes, slave supports 8, 16, and

32-bit transfer sizes

The AXI interface has the following features:

❖ AXI Master and Slave for AHCI programming and PDMA requests

❖ All types of AHCI transactions supported through the AXI BIU

❖ Independently configurable AXI master and slave address widths, data bus widths, and ID bus

widths

❖ Number of DMA outstanding read requests limited by PRD size, FIS size, data bus width, and bus

beat configuration

❖ All burst-sizes supported for both AXI master and slave interfaces (within address space)

❖ Programmable/extended burst lengths to support up to 4K read/write burst lengths over AXI

master interface

❖ Unaligned AXI transfers using WSTRB for both AXI master and slave interfaces

The Generic Register module implements all DWC_ahsata global registers and provides the following

functions:

❖ Generic configuration and control;

❖ Global interrupt support;

❖ BIST operation (DWC_ahsata-specific registers).

1.3.4 Port DMA and Register Modules Overview

The controller includes two Port Modules: a Port DMA module, and a Port Register module.

The Port DMA module provides the following functions:

❖ Detects and processes commands posted by the software to the Command List, transfers

corresponding Register Frame Information Structures (FISes) to the Transport Layer;

❖ Receives FISes from the Transport Layer and transfers them to the system memory;

❖ Transfers data between the Transport Layer FIFOs and system memory;

❖ Provides Native Command Queueing (First-Party DMA);

❖ Supports power management including Rx and Tx clock removal in power modes. (Refer to Note

regarding removal of clocks in power modes under “Power Management” on page 22).

NoteNoteNoteNote

M_BURST_TYPE configuration parameter determines the AHB Master burst type:

• When configured for Fixed, only SINGLE, INCR4, INCR8, and INCR16 burst types are used.

• When configured for Unspecified, only INCR burst type is used for all transfers.

NoteNoteNoteNote

• Do not remove application clock (hclk/aclk) in power modes.

• See the cautionary note on page 79 regarding clock restoration requirements when clocks are

removed during power modes.

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